Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-01-29
2008-01-29
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S427000, C257SE21548
Reexamination Certificate
active
11050988
ABSTRACT:
An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
REFERENCES:
patent: 5198995 (1993-03-01), Dennard et al.
patent: 5267201 (1993-11-01), Foss et al.
patent: 5297104 (1994-03-01), Nakashima
patent: 5371705 (1994-12-01), Nakayama et al.
patent: 5377139 (1994-12-01), Lage et al.
patent: 5394365 (1995-02-01), Tsukikawa
patent: 5416034 (1995-05-01), Bryant
patent: 5449636 (1995-09-01), Park et al.
patent: 5600598 (1997-02-01), Skjaveland et al.
patent: 5694355 (1997-12-01), Skjaveland et al.
patent: 5703827 (1997-12-01), Leung et al.
patent: 5789291 (1998-08-01), Sung
patent: 5863819 (1999-01-01), Gonzalez
patent: 5963838 (1999-10-01), Yamamoto et al.
patent: 5986947 (1999-11-01), Choi et al.
patent: 5999474 (1999-12-01), Leung et al.
patent: 6002606 (1999-12-01), Komatsu
patent: 6009023 (1999-12-01), Lu et al.
patent: 6104055 (2000-08-01), Watanabe
patent: 6147914 (2000-11-01), Leung et al.
patent: 6333532 (2001-12-01), Davari et al.
patent: 6352890 (2002-03-01), Sutcliffe
patent: 6406976 (2002-06-01), Singh et al.
patent: 6468855 (2002-10-01), Leung et al.
patent: 6492224 (2002-12-01), Jao
patent: 7019348 (2006-03-01), Tu
patent: 2002/0053691 (2002-05-01), Leung et al.
patent: 3543937 (1986-06-01), None
patent: 4034169 (1991-05-01), None
patent: 460694 (1991-12-01), None
patent: 493659 (1992-07-01), None
patent: 632462 (1995-01-01), None
patent: 60113461 (1985-06-01), None
patent: 01150353 (1989-06-01), None
patent: 03136275 (1991-06-01), None
patent: 3259566 (1991-11-01), None
patent: 7094596 (1995-04-01), None
patent: 8063964 (1996-03-01), None
patent: WO 01/01450 (2001-01-01), None
Gillingham et al. “A 768k Embedded DRAM for 1.244Gb/s ATM Switch in a 0.8um Logic Process”, 1996 IEEE Int'l. Solid-State Circuits Conf. (2pgs).
Hashimoto et al. “An Embedded DRAM Module using a Dual Sense Amplifier Architecture in a Logic Process”, 1997 IEEE Int'l. Solid-State Circuits Conf. (3 pgs).
Gray et al. “Chap 4-Transistor Current Sources and Active Loads”, Analysis And Design Of Analog Integrated Circuits, pp. 330-333, no date.
Hsu Fu-Chieh
Sinitsky Dennis
Bever Hoffman & Harms LLP
Chaudhari Chandra
Hoffman, Esq. E. Eric
MoSys, Inc.
LandOfFree
Fabrication process for increased capacitance in an embedded... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication process for increased capacitance in an embedded..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication process for increased capacitance in an embedded... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3956076