Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-01-29
2008-01-29
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S427000, C257SE21548
Reexamination Certificate
active
07323379
ABSTRACT:
An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
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Hsu Fu-Chieh
Sinitsky Dennis
Bever Hoffman & Harms LLP
Chaudhari Chandra
Hoffman, Esq. E. Eric
MoSys, Inc.
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