Fabrication process for aligned and stacked CMOS devices

Details Fabrication process for aligned and stacked CMOS devices Fabrication process for aligned and stacked CMOS devices

1986-02-27

1987-03-31

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

148 15, 148187, 148191, 29571, 29576B, 29576W, 29591, 156657, 1566591, 156668, 357 2311, 357 41, 357 59, 357 91, B44C 122, H01L 2122, H01L 2702, C03C 1500

Patent

active

046541217

ABSTRACT:
A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regions of the lower FET device. A planarizing photoresist is then deposited and etched in conjunction with the oxide to the upper surface of the gate electrode. The exposed gate electrode is covered with a gate oxide layer, and a polycrystalline silicon layer for recrystallization to an upper FET device. Updiffusion from the residuals of doped oxide then creates an upper FET device with source and drain regions aligned to the gate oxide thereof and the underlying common gate electrode.

REFERENCES:
patent: 4514233 (1985-04-01), Kawabuchi
patent: 4545852 (1985-10-01), Barton
patent: 4603468 (1986-08-01), Lam
Hite et al., "Process and Performance Comparison of an 8K.times.8-Bit SRAM in Three Stacked CMOS Technologies", IEEE, Oct. 1985, 548-50.

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