Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-14
2004-06-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S272000, C438S430000, C438S431000
Reexamination Certificate
active
06756274
ABSTRACT:
BACKGROUND
FIG. 1
illustrates a conventional vertical double-diffused MOSFET (DMOS)
10
with a trench gate
11
, a diffused P-type body diffusion (P
B
), a shallow N+ source region
12
, a P+ body contact region
13
, formed in an N-type epitaxial layer N
epi
grown on an N+ substrate. A source metal
14
, using a butting contact structure, shorts the source and body contact regions
12
and
13
. The gate
11
is embedded in a trench
15
etched into the epitaxial layer N
epi
, oxidized and then filled with doped polysilicon. The channel of the device is formed along the sidewall of the trench in the silicon region extending between the N+ source-to-P
B
body junction to the junction formed between the P
B
body and the N-type epitaxial drain. In conventional devices, the gate oxide
16
on the trench sidewalls and bottom is formed simultaneously and is therefore of uniform thickness (except for the subtle variations due to compressive oxidation effects on curved surfaces and differing oxidizing rates on various crystallographic planes).
The drain doping is typically lower in concentration than the P
B
body region so as to provide substantial depletion spreading in the drain and minimal depletion spreading in the channel for any applicable voltage. The heavier doping in the P
B
body avoids punchthrough breakdown and other undesirable effects of the short channel, which normally has an effective length of 0.3 to 1 &mgr;m.
The on-resistance of such a device is determined by the sum of its resistive components shown in
FIG. 2
, namely its substrate resistance (R
sub
), its epitaxial drain resistance (R
epi
), its channel resistance (R
ch
), its source contact resistance (R
c
), and its metal interconnect resistance (R
M
). The epitaxial resistance (R
epi
) is subdivided between a region where current emanating from the channel is spreading out (R
epi1
) and, in the case of thicker epitaxial layers, another region where the current has become uniform (R
epi2
).
R
DS
=R
M
+R
c
+R
ch
+R
epi
+R
sub
(1)
where
R
epi
=R
epi1
+R
epi2
(2)
The primary design goal for a power MOSFET used as a switch is to achieve the lowest on-resistance by simultaneously minimizing each of its resistive constituents. The following factors must be considered:
1. The metal resistance is minimized through the use of a thicker metal layer.
2. Grinding the wafer to the thinnest possible dimension minimizes the substrate resistance. The grinding must be performed near the end of the fabrication process so that the risk of breakage from handling is minimized.
3. There is an unavoidable tradeoff between the avalanche breakdown voltage and the on-resistance of the device. Higher breakdown voltages require thicker, more lightly doped epitaxial layers contributing higher epitaxial resistances. Generally, the doping of the epitaxial layer is chosen so as to provide the most highly-doped layer capable of supporting the required off-state blocking voltage (i.e., its specified avalanche breakdown voltage).
4. The channel resistance is minimized by maximizing the channel perimeter for a given area. The individual cells of the MOSFET may be constructed in any striped or polygonal shape. Ideally, the shape chosen should be one that can be repeated at a regular pitch so that more cells can be connected in parallel in a given area. Paralleling many cells and operating them in tandem can achieve an extremely low on-resistance.
5. Higher cell densities have the advantage that the current in the epitaxial drain becomes uniform closer to the surface, more fully utilizing the epitaxial layer for conduction and reducing the spreading resistance term (R
epi1
) of the epitaxial resistance. As may be seen be by comparing
FIG. 3A
with
FIG. 3B
, a smaller cell pitch reduces the area wasted where no current flows, conducting current uniformly through a greater percentage of the total thickness of the epitaxial layer. The more uniform conducting epitaxial layer exhibits a lower drain resistance.
Maximizing the perimeter of the trench gate for a given area lowers the channel resistance (R
ch
), since the equation for the MOSFET channel conduction depends on the total “perimeter” of the gate, not the area of the device.
The equation for the channel resistance of a conventional lateral MOSFET can be used to approximate the channel resistance of a vertical DMOS.
R
ch
=
1
μ
·
C
ox
·
W
L
ch
·
(
V
GS
-
V
t
)
where
(
3
)
C
ox
=
ϵ
ox
χ
ox
combining
·
gives
(
4
)
R
ch
·
W
=
1
μ
·
C
ox
·
1
L
ch
·
(
V
GS
-
V
t
)
(
5
)
Expressed in terms of area using the geometric figure of merit A/W yields the form
R
ch
A
=
R
ch
W
·
A
W
whereby
(
6
)
R
ch
A
=
1
μ
·
C
ox
·
1
L
ch
·
(
V
GS
-
V
t
)
·
A
W
(
7
)
Since it is desirable to maximize W and minimize A, the figure of merit A/W needs to be reduced to lower the channel resistance. To determine the A/W for various cell geometries, the equations for area A and perimeter W can be defined in terms of the trench width (the surface dimension Y
G
of the trench, as distinguished from the “gate width W”) and the width Y
SB
of the source-body “mesa” between trenches. For the continuous stripe of surface length Z, as shown in
FIG. 4A
, we have
A=Z·
(
Y
G
+Y
SB
) (8)
and
W=2Z (9)
yielding
A
W
=
(
Y
G
+
Y
SB
)
2
(
10
)
In other words, the A/W for a stripe geometry is simply one-half of the pitch. For the square cell of
FIG. 4B
, the perimeter is
A=
(
Y
G
+Y
SB
)
2
(11)
and
W=4Y
SB
(12)
so
A
W
=
(
Y
G
+
Y
SB
)
2
4
Y
SB
(
13
)
Compared to the stripe geometry, the square cell geometry offers a lower resistance whenever the gate is small compared to the source-body dimension. Since in a conventional trench-gated DMOS, manufacturing a small trench is not as difficult as manufacturing a small silicon mesa, the closed cell geometry is superior in performance. In the event that the gate dimension is larger than the source-body mesa dimension, the stripe geometry offers superior performance. This circumstance is difficult to achieve in practice, especially in narrow trench gate designs where the alignment tolerances needed to form the source and body regions and to establish a contact to them leads to a wide mesa. Whenever the gate dimension Y
G
and the source-body mesa dimension Y
SB
are equal, there is no difference between the two geometries in terms of minimizing A/W.
The presence of a source at the square corners in an array of trench-gated DMOS cells has been found to lead to off-state leakage in the device, possibly due to defects along the trench corners or some enhanced diffusion of the source along the corners. One solution to this problem is to block the N+ source from being implanted into the corners of the trench using a photoresist mask, as shown in FIG.
4
C. Unfortunately, this corner block feature reduces the gate perimeter of the device and increases channel resistance. Assume the donut-shaped source has a width of Y
S
, which necessarily must be less than half the mesa width Y
SB
. If we remove only the corners from the source mask as shown, the perimeter of the device is no longer 4Y
SB
, but drops to
W
=4·(
Y
SB
−Y
S
) (14)
so
A
W
=
(
Y
SB
+
Y
G
)
2
4
·
(
Y
SB
-
Y
S
)
(
15
)
The predicted resistance penalty due to the corner block is linear, so if Y
S
is 20% of Y
SB
, the gate perimeter is reduced by 20% and the channel resistance is increased accordingly. This explanation is a worst-case model since it assumes no conduction in the corner-blocked region. In reality, some current flows in the corner blocked regions, but they correspond to a transistor having a longer channel length and possibly a different threshold voltage. Furthe
Grabowski Wayne
Williams Richard K.
Advanced Analogic Technologies, Inc.
Masawma Lex H.
Millers David T.
Smith Matthew
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