Fabrication process for a novel multi-storage EEPROM cell

Details Fabrication process for a novel multi-storage EEPROM cell Fabrication process for a novel multi-storage EEPROM cell

1997-10-06

1999-06-29

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438267, 438596, H01L 218247

Patent

active

059181249

ABSTRACT:
A EEPROM cell design, and a method of fabrication for the EEPROM cell, has been developed. The EEPROM cell includes a polysilicon control gate structure, polysilicon select gate structures, and novel polysilicon, floating gate spacer structures, fabricated using deposition and anisotropic etching, sidewall processes. The use of floating gate spacers, allows density improvements to be realized. The EEPROM cell can programmed, read, and erased, using only biasing conditions, without having to use UV light for the erase cycle.

REFERENCES:
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5354702 (1994-10-01), Arima et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5529945 (1996-06-01), Rao
patent: 5614747 (1997-03-01), Ahn et al.

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