Fabrication process for a lower electrode of a memory capacitor

Details Fabrication process for a lower electrode of a memory capacitor Fabrication process for a lower electrode of a memory capacitor

2000-07-21

2001-11-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000, C438S964000

Reexamination Certificate

active

06319771

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a fabrication process for a memory device. More particularly, the present invention relates to a fabrication process for a lower electrode of a memory capacitor.
2. Description of the Related Art
A capacitor is an important component of a dynamic random access memory (DRAM). In order to avoid mistakes in information stored in the DRAM, and to increase the operation efficiency of the DRAM, a three-dimensional capacitor having a large area, such as the common cylinder capacitor, is usually fabricated.
The conventional fabrication process for a lower electrode of a cylinder capacitor is as follows. First, a first insulating layer is formed on the substrate. Then, a node contact that has electrical connection with the substrate is formed in the first insulating layer. Afterwards, a second insulating layer is formed on the first insulating layer. An opening which exposes the node contact is provided in the second insulating layer. Then, a conductive layer, which functions as the lower electrode of the cylinder capacitor, is formed on the inner wall and the bottom of the opening. In the conventional fabrication process for a lower electrode of a cylinder capacitor, the template that forms the node contact and the lower electrode of a cylinder capacitor and the opening of the second insulating layer each require a photomask process. Thus two photomask processes are necessary. As a result, the conventional process not only wastes time, but also easily causes alignment problems.
SUMMARY OF THE INVENTION
The present invention provides a fabrication process for a lower electrode of a cylinder capacitor whose surface area is larger than that provided by the conventional technology and only requires one photomask process. The steps of the process are as follows. A first insulating layer is formed on a substrate. A self-aligned contact opening is formed in the first insulating layer, which opening exposes a conducting area on the substrate. Then, the first conductive layer is formed on the first insulating layer and in the self-aligned contact opening. The first conductive layer is conformal to the first insulating layer having the self-aligned contact opening. At this point the first conductive layer below the self-aligned contact opening is a contact. Afterwards, the self-aligned contact opening is filled with a second insulating layer and the first conductive layer is back-etched in order to remove completely the first conductive layer that is outside the self-aligned contact opening and to remove the first conductive layer to a certain depth inside the self-aligned contact opening. Afterwards, the second conductive layer is formed on the sidewalls of the first and the second insulating layers that are in the self-aligned contact opening. This second conductive layer functions as a lower electrode of a capacitor.
As described above, in the fabrication process for a lower electrode of a memory capacitor according to the present invention, the second conductive layer that functions as the main body of a lower electrode of a memory capacity is formed not only on the inner sidewall of the self-aligned contact opening, but also on the sidewall of second insulating layer that is at the center of the self-aligned contact opening. Therefore, the surface area of the lower electrode of the memory capacitor obtained through the process according the present invention is larger than that of the lower electrode of a cylinder capacitor obtained through the conventional process. In addition, because the template of the lower electrode of the capacitor in the present process is the upper part of the self-aligned contact opening, the forming of the node contact and the lower electrode of the capacitor requires only one photomask process for defining the self-aligned contact opening.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, only, and are not restrictive of the invention as claimed.


REFERENCES:
patent: 6146961 (2000-11-01), Graettinger et al.
patent: 6261190 (2001-07-01), Tseng

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