Fabrication process and structure of laminated capacitor

Details Fabrication process and structure of laminated capacitor Fabrication process and structure of laminated capacitor

2003-05-20

2004-04-06

Niebling, John (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S250000, C438S253000, C438S396000, C438S393000, C438S122000, C361S321200, C361S321300, C361S321400

Reexamination Certificate

active

06716692

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91136482, filed on Dec. 18, 2002.
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates in general to a fabrication process and a structure of a laminated capacitor, and more particularly, to a fabrication process which uses high-speed physical metal deposition and dielectric material coating to form multiple electrode layers and dielectric layers, respectively, alternately stacked to form a laminated capacitor structure.
2. Related Art of the Invention
With the advancement of semiconductor techniques, more sophisticated and advanced electronic devices have been developed based on the enhanced market demand of semiconductor assembly products. For example, the technique of flip-chip assembly, the design of laminated substrates and passive devices play important roles in semiconductor industry. In the example of flip-chip/ball grid array package structures, the chip is arranged on a surface of a package substrate and electrically connected thereto. The package substrate is typically integrated with multiple patterned wiring layers and multiple insulation layers. The patterned wiring layers can be formed through photolithography and etching steps, and the insulation layers are formed between two neighboring patterned wiring layers. In addition, to obtain better electrical performance, passive devices such as capacitors, inductors and resistors are formed on the package substrate and electrically connected to the chip and other electronic devices via an internal wiring of the package substrate.
In a high-speed operation of the chip, heat is generated from the passive devices. The heat generated from the chip is delivered to the package substrate and the passive devices. To allow the passive devices to operate normally without affecting the electric characteristics thereof even under a high-temperature environment, high-temperature endurable and highly stable passive devices have to be designed. The laminated ceramic capacitor is one such passive device.
The conventional laminated capacitor is typically constructed by stacking a plurality of dielectric layers and metallic layers. The ceramic dielectric layers are normally formed of materials with high dielectric constant such as barium titanate, while the metallic layers are typically made of conductive materials such as silver and silver-protactinium alloy. The metallic layers form a plurality of alternate positive and negative internal electrodes. A capacitor structure is thus formed with the internal electrodes and the ceramic dielectric layers. A pair of terminal electrodes is further formed at two sides of the metallic layers to electrically connect the positive and negative internal electrodes, respectively. A surface metal layer such as a nickel layer is formed on the surface of each terminal electrode to prevent oxidizing the terminal electrodes.
In addition, the process of the conventional laminated capacitor further comprises the following steps. A process of ceramic green tape is performed. In this process, dielectric powder such as barium titanate is uniformly mixed with organic binder to form a ceramic green tape. A metal paste printing process that uses screen printing to transfer metal powder and organic binder on the ceramic green tape to form a metal layer is performed. The processes of stacking and pressing are then performed on the ceramic green tape to form a structure laminated with multiple ceramic dielectric layers and metallic layers. The laminated structure is then disposed in a sinter temperature between 1100° C. and 1500° C. to perform sinter. A pair of terminal electrodes is then formed at two sides of the structure with ceramic dielectric layers and metallic layers that have been sintered. A sinter process is further performed to cure the terminal electrodes to complete the process of fabricating the laminated capacitor.
In the above sinter process, the organic solvent is evaporated during high-temperature sintering, such that the volume of the ceramic dielectric layers and the metallic layers are shrunk, affecting the junction connectivity thereof. Further, the thickness of the ceramic dielectric layers and the metallic layers cannot be consistent with each other, such that the capacitance cannot be controlled within the standard. In addition, in the sinter process, the thermal expansion coefficient of the metallic layers is different from that of the ceramic dielectric layers, and the optimum sintering temperature of the metallic layers is different from that of the ceramic dielectric layers, cracks, voids, seams, peels and delaminates may occur in the laminated capacitor to seriously affect the standard capacitance thereof.
SUMMARY OF INVENTION
The present invention provides a fabrication process and a method of a laminated capacitor. The laminated capacitor is formed under a constant temperature, such that the thickness of the dielectric layers and the adhesion layers are uniform. Further, the connectivity between the dielectric layers and the metallic layers is improved, and the capacitance of the laminated capacitor is controlled within the standard range.
The fabrication process of a laminated capacitor provided by the present invention comprises the following steps. A substrate is provided. A first masking layer is formed on the surface of the substrate. A step of high-speed physical deposition is performed to form a first electrode layer on the substrate surface exposed by the first masking layer. The first masking layer is removed. A first dielectric layer is formed on the first dielectric layer and the first electrode layer using dielectric material coating. A patterned second masking layer is formed on the first dielectric layer. A step of high-speed metal deposition is performed to form a second electrode layer on the first electrode layer exposed by the second masking layer. Thereby, the second electrode layer and the first electrode layer are at least partially overlapped with each other. The second masking layer is then removed.
According to the fabrication process provided by the present invention, two electrode layers may be formed. By repeating the steps for forming the patterned first masking layer to the step for removing the first masking layer once, three electrode layers are formed. By performing the step for forming the patterned first masking layer to the step of removing the second masking layer at least once, an even number (2N) of electrode layers is formed. After an even number of electrode layers is formed, by performing the step for forming the patterned first masking layer to the step of removing the first masking layer once again, an odd number of electrode layers (2N+1) is formed.
The above fabrication process further comprises the following steps. A second dielectric layer is formed on the second electrode layer and a topmost dielectric layer of the first dielectric layers. A pair of terminal electrodes is formed on two sides of the first electrode layers and the second electrode layers to electrically connect the first and second electrodes, respectively. A surface metal layer is formed on the exposed surface of the terminal electrodes.
The present invention further comprises a laminated capacitor comprising a plurality of electrode layers and at least one dielectric layer. Any two neighboring electrode layers are partially overlapped with each other, and the relative horizontal displacement between any neighboring two of the electrode layers is smaller than 100 microns. In addition, dielectric layers can be formed between any two neighboring dielectric layers with a thickness uniformity maintained at about ∈±10%.


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