Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-14
2008-08-26
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C257SE21623
Reexamination Certificate
active
07416949
ABSTRACT:
Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.
REFERENCES:
patent: 2004/0245583 (2004-12-01), Horiuchi et al.
patent: 2006/0019437 (2006-01-01), Murto et al.
patent: 2007/0218637 (2007-09-01), Harada et al.
patent: 2007/0275528 (2007-11-01), Koike
Kittle, et al., “Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 72-73.
Pas Michael Francis
Yu Shaofeng
Ahmadi Mohsen
Brady III Wade J.
Geyer Scott B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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