Fabrication of test field effect transistor structure

Details Fabrication of test field effect transistor structure Fabrication of test field effect transistor structure

2001-05-01

2002-08-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000

Reexamination Certificate

active

06436773

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors, and more particularly, to fabrication of a test field effect transistor having a large width formed from a perimeter of a shaped area, using a minimized number of processing steps for minimized contamination.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
farther includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
A new material may be developed for forming a structure of the MOSFET such as a new material for the gate dielectric
116
or for the gate electrode
118
. The operation of a MOSFET with such new material is tested before using such new material in integrated circuit products. A mechanism is desired for fabricating a test MOSFET with such new material to test the operation of a MOSFET with the new material. The test MOSFET is desired to be fabricated with a relatively minimized number of fabrication steps to reduce contamination and is desired to have a relatively large width such that current crowding effects and parasitic resistance are not significant factors during testing of the operation of the MOSFET. Current crowding effects and parasitic resistance of a MOSFET, which are known to one of ordinary skill in the art of integrate circuit fabrication, degrade the proper operation of the MOSFET to obscure testing of the operation of the field effect transistor with a new material for a structure of the field effect transistor.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a test field effect transistor is fabricated with a large width formed from a perimeter of a shaped area, using a minimized number of processing steps for minimized contamination.
In one embodiment of the present invention, in a method for fabricating a test field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A dummy structure is formed on the gate electrode material, and the dummy structure is disposed over a shaped area of the gate electrode material and of the semiconductor substrate. The dummy structure has at least one sidewall around a perimeter of the shaped area. A spacer structure is formed to surround the at least one sidewall of the dummy structure outside of the perimeter of the shaped area, and the spacer structure has a width extending out from the perimeter of the shaped area. The dummy structure is etched away such that the shaped area of the gate electrode material is exposed and such that the spacer structure remains outside of the perimeter of the shaped area.
Any exposed regions of the gate electrode material and of the gate dielectric material not under the spacer structure are etched away. The gate dielectric material remaining under the spacer structure forms a gate dielectric of the test field effect transistor, and the gate electrode material remaining under the spacer structure forms a gate electrode of the test field effect transistor. The gate dielectric and the gate electrode are formed outside of the perimeter of the shaped area on the semiconductor substrate. A drain and source dopant is implanted into exposed regions of the semiconductor substrate to form a first drain or source junction from the drain and source dopant being implanted into the semiconductor substrate within the shaped area surrounded by the gate dielectric and the gate electrode, and to form a second drain or source junction from the drain and source dopant being implanted into the semiconductor substrate outside the shaped area beyond the gate dielectric and the gate electrode. A width of the test field effect transistor is the perimeter of the shaped area, and a length of the test field effect transistor is the width of the gate dielectric and the gate electrode extending out from the perimeter of the shaped area.
The present invention may be used to particular advantage when the shaped area is a circular shape having a diameter of about 0.5 micrometers, and when the dummy structure is comprised of silicon nitride (Si
3
N
4
) with the spacer structure being comprised of silicon dioxide (SiO
2
).
In this manner, the test field effect transistor structure is fabricated with a relatively few processing steps. A processing step increases the probability for contamination of the test field effect transistor. Thus, fewer processing steps minimize contamination of the test field effect transistor. Minimized contamination is desired because failure of the test field effect transistor from contamination obscures testing of the operation of the field effect transistor with a new material for a structure of the field effect transistor. In addition, the width of the field effect transistor around the perimeter of the shaped area is relatively large to minimize current crowding effects and to minimize parasitic resistance of the field effect transistor. Current crowding effects and parasitic resistance of a field effect transistor degrade the proper operation of the field effect transistor to obscure testing of the operation of the field effect transistor with a new material for a structure of the field effect transistor.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.


REFERENCES:
patent: 3696273 (1972-10-01), Foster
patent: 5753942 (1998-05-01), Seok
patent: 5847413 (1998-12-01), Yamazaki et al.
patent: 5923981 (1999-07-01), Qian
patent: 5956608 (1999-09-01), Khurana et al.
patent: 6153978 (2000-11-01), Okamoto
patent: 6214681 (2001-04-01), Yu
patent: 6242321 (2001-06-01), Acosta et al.

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