Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-31
2010-11-23
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C257SE27060
Reexamination Certificate
active
07838369
ABSTRACT:
An insulated-gate field-effect transistor (100, 100V,140, 150, 150V,160, 170, 170V,180, 180V,190, 210, 210W,220, 220U,220V,220W,380, or480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104or264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108or268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120or280) situated along the other source/drain zone (102or262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.
REFERENCES:
patent: 5364807 (1994-11-01), Hwang
patent: 5963801 (1999-10-01), Aronowitz et al.
patent: 6078082 (2000-06-01), Bulucea
patent: 6127700 (2000-10-01), Bulucea
patent: 6548842 (2003-04-01), Bulucea et al.
patent: 6566204 (2003-05-01), Wang et al.
patent: 6576966 (2003-06-01), Bulucea et al.
patent: 6621125 (2003-09-01), Wang
patent: 6927116 (2005-08-01), Arai
patent: 7145191 (2006-12-01), Teng et al.
patent: 7176530 (2007-02-01), Bulucea et al.
patent: 7235450 (2007-06-01), Kim
patent: 2004/0188767 (2004-09-01), Weber et al.
Buti et al., “Asymmetrical Halo Source GOLD drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance”,IEDM Tech. Dig., Dec. 3-6, 1989, pp. 26.2.1-26.2.4.
Chai et al., “A Cost-Effective 0.25 μm LeffBiCMOS Technology Featuring Graded-Channel CMOS (GCMOS) and a Quasi-Self-Aligned (QSA) NPN for RF Wireless Applications”,Procs. 2000 Bipolar/BiCMOS Circs. and Tech. Meeting, Sep. 24-26, 2000, pp. 110-113.
Cheng et al., “Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Submicron CMOS”,1999 Symp. VLSI Tech., Dig. Tech. Paps., Jun. 14-16, 1999, pp. 69 and 70.
Deshpande et al., “Channel Engineering for Analog Device Design in Deep Submicron CMOS Technology for System on Chip Applications”,IEEE Trans. Elec. Devs., Sep. 2002, pp. 1558-1565.
Dolny et al., “Enhanced CMOS for Analog-Digital Power IC Applications”,IEEE Trans. Elec. Devs., 1986, pp. 1985-1991.
Gray et al.,Analysis and Design of Analog Integrated Circuits(4th ed., John Wiley & Sons), 2001, pp. 49-65.
Hiroki et al, “A High Performance 0.1 μm MOSFET with Asymmetric Channel Profile”,IEDM Tech. Dig., Dec. 1995, pp. 17.7.1-17.7.4.
Lamey et al., “Improving Manufacturability of an RF Graded Channel CMOS Process for Wireless Applications”, SPIE Conf. Microelec. Dev. Tech. II, Sep. 1998, pp. 147-155.
Ma et al., “Graded-Channel MOSFET (GCMOSFET) for High Performance, Low Voltage DSP Applications”,IEEE Trans. VLSI Systs. Dig., Dec. 1997, pp. 352-358.
Matsuki et al., “Laterally-Doped Channel (LDC) Structure for Sub-Quarter Micron MOSFETs”,1991 Symp. VLSI Tech., Dig. Tech. Paps., May 28-30, 1991, pp. 113 and 114.
Odanaka et al., “Potential Design and Transport Property of 0.1-μm MOSFET with Asymmetric Channel Profile”,IEEE Trans. Elec. Devs., Apr. 1997, pp. 595-600.
Shimizu et al., “High Drivability CMOSFETs with Asymmetrical Source-Drain (ASD) Structure for Low Supply Voltage ULSIs”,Ext'd Abstrs, 21st Conf. Solid State Devs. and Mats., 1989, pp. 125-128.
Su et al., “A High-Performance Scalable Submicron MOSFET for Mixed Analog/Digital Applications”,IEDM Tech. Dig., Dec. 1991, pp. 367-370.
Le Thao P.
Meetin Ronald J.
National Semiconductor Corporation
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