Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-26
2001-05-08
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S981000
Reexamination Certificate
active
06228721
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of field effect transistors with gate dielectrics of metal oxide structures of different thicknesses on a semiconductor substrate.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
Conventionally, the gate dielectric
116
for the MOSFET
100
is typically comprised of silicon dioxide (SiO
2
), and the gate electrode
118
is typically comprised of polysilicon. As the channel length and width dimensions of the MOSFET
100
are scaled down for enhanced speed performance, the thicknesses of the gate dielectric
116
and the gate electrode
118
are also correspondingly scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as the channel length and width dimensions of the MOSFET
100
are scaled down to tens of nanometers, the thickness of the gate dielectric
116
is also scaled down to tens of angstroms when the gate dielectric
116
is comprised of silicon dioxide (SiO
2
). With such a thin gate dielectric
116
, charge carriers easily tunnel through the gate dielectric
116
, as known to one of ordinary skill in the art of integrated circuit fabrication.
When charge carriers tunnel through the gate dielectric
116
, gate leakage current undesirably increases resulting in increased static power dissipation and even circuit malfunction. In addition, with charge carriers tunneling through the gate dielectric
116
, decreased charge carrier accumulation in the channel of the MOSFET may result in undesirable increase in resistance through the channel of the MOSFET. Furthermore, with the thin gate dielectric
116
, the charge accumulation at the gate electrode
118
causes an undesirable increase in charge carrier scattering at the surface of the channel of the MOSFET
100
. Such increase in charge carrier scattering in turn results in higher resistance through the channel of the MOSFET.
In light of these disadvantages of the thin gate dielectric
116
when the gate dielectric
116
is comprised of silicon dioxide (SiO
2
), a gate dielectric having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
) (i.e., a high dielectric constant material) is used for a field effect transistor having scaled down dimensions of tens of nanometers. A dielectric material having a higher dielectric constant has higher thickness for achieving the same capacitance. Thus, when the gate dielectric is comprised of a high dielectric constant material, the gate dielectric has a higher thickness (hundreds of angstroms) than when the gate dielectric is comprised of silicon dioxide (SiO
2
) (tens of angstroms), for field effect transistors having scaled down dimensions of tens of nanometers.
The gate dielectric with high dielectric constant has higher thickness to minimize charge carrier tunneling through the gate dielectric for field effect transistors having scaled down dimensions of tens of nanometers. Examples of dielectric materials with high dielectric constant include metal oxides such as aluminum oxide (Al
2
O
3
), titanium dioxide (TiO
2
), or tantalum oxide (Ta
2
O
5
). Such dielectric materials are usually deposited or sputtered onto the semiconductor substrate in the prior art. However, with the deposition and sputtering processes of the prior art, the uniformity of thickness of such dielectric materials for formation of gate dielectrics having scaled down dimensions of hundreds of angstroms is typically unacceptable. In addition, the metal oxides are typically difficult to etch. For example, in a wet etch process, metal residue from the etched metal oxide may undesirably contaminate the semiconductor substrate.
Furthermore, metal oxide structures with different thicknesses may be desired on the same semiconductor substrate. A gate dielectric comprised of a metal oxide structure having a smaller thickness is desired for a MOSFET with a lower threshold voltage for enhanced speed performance of such a MOSFET. On the other hand, a gate dielectric comprised of a metal oxide structure having a larger thickness is desired for a MOSFET with a higher threshold voltage for low-power applications with such a MOSFET.
Thus, a mechanism is desired for effectively fabricating metal oxide structures with different thicknesses on the same semiconductor substrate for use as gate dielectrics of field effect transistors having scaled down dimensions of tens of nanometers.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a metal oxide structure is fabricated by forming an opening on top of a layer of metal and with localized thermal oxidation of the layer of metal exposed at the opening.
In one embodiment of the present invention, in a method for fabricating at least one metal oxide structure on a semiconductor substrate, a first active device area surrounded by at least one STI (shallow trench isolation) structure is formed in the semiconductor substrate. A first layer of metal is deposited on the semiconductor substrate, and the first layer of metal contacts the first active device area of the semiconductor substrate. A first layer of oxygen blocking material is deposited on the first layer of metal. A first opening is etched through the first layer of oxygen blocking material to expose a first area of the first layer of metal on top of the fir
Advanced Micro Devices , Inc.
Chaudhari Chandra
Choi Monica H.
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