Fabrication of local interconnect lines

Details Fabrication of local interconnect lines Fabrication of local interconnect lines

2007-04-24

2007-04-24

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S618000, C438S700000, C438S714000, C438S734000, C257SE27108, C257SE21632, C257SE21249

Reexamination Certificate

active

11123833

ABSTRACT:
A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure at a second temperature lower than the first temperature to extend the holes and slits to devices of the CMOS structure.

REFERENCES:
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patent: 6274471 (2001-08-01), Huang
patent: 2003/0036227 (2003-02-01), Hohnsdorf
patent: 2005/0101034 (2005-05-01), Aggarwal et al.
patent: 2005/0200026 (2005-09-01), Liaw
patent: 2005/0245074 (2005-11-01), Jiang et al.

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