Fabrication of local damascene finFETs using contact type...

Details Fabrication of local damascene finFETs using contact type... Fabrication of local damascene finFETs using contact type...

2011-03-08

2011-03-08

Garber, Charles D (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29264

Reexamination Certificate

active

07902607

ABSTRACT:
Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices.

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Office Action for Chinese patent application No. 200610144646.2 dated Jul. 18, 2008 and English translation thereof.

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