Fabrication of germanium nanowire transistors

Details Fabrication of germanium nanowire transistors Fabrication of germanium nanowire transistors

2007-12-31

2010-06-01

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S588000, C257S066000, C257S331000, C257S347000, C257SE21112, C257SE29264, C257SE21421

Reexamination Certificate

active

07727830

ABSTRACT:
In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

REFERENCES:
patent: 7588977 (2009-09-01), Suk et al.
patent: 7622773 (2009-11-01), Irisawa et al.
patent: 2008/0237575 (2008-10-01), Jin et al.
patent: 2009/0085027 (2009-04-01), Jin et al.

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