Fabrication of field effect transistor with shallow...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S308000, C438S303000, C438S301000

Reexamination Certificate

active

06893930

ABSTRACT:
For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on the active device area of the semiconductor substrate. Antimony (Sb) dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form at least one of drain and source extension junctions and/or drain and source contact junctions. A low temperature thermal anneal process at a temperature less than about 950° Celsius is performed for activating the antimony (Sb) dopant within the drain and source extension junctions and/or drain and source contact junctions. In one embodiment of the present invention, the drain and source contact junctions are formed and thermally annealed before the formation of the drain and source extension junctions in a disposable spacer process for further minimizing heating of the drain and source extension junctions. In another embodiment of the present invention, the drain and source extension junctions and/or the drain and source contact junctions are formed to be amorphous before the thermal anneal process. In that case, a SPE (solid phase epitaxy) activation process in performed for activating the antimony (Sb) dopant within the amorphous drain and source extension junctions and/or the amorphous drain and source contact junctions at a temperature less than about 650° Celsius.

REFERENCES:
patent: 5973372 (1999-10-01), Omid-Zohoor et al.
patent: 6380044 (2002-04-01), Talwar et al.
patent: 6429054 (2002-08-01), Krishnan et al.
patent: 6465847 (2002-10-01), Krishnan et al.
patent: 6472282 (2002-10-01), Yu

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