Fabrication of field effect transistor with dual laser...

Details Fabrication of field effect transistor with dual laser... Fabrication of field effect transistor with dual laser...

2001-06-01

2003-05-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S311000, C438S306000

Reexamination Certificate

active

06559015

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor using dual laser thermal anneal processes for activating dopant within the contact junctions and the extension junctions of the field effect transistor.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET ID (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET
100
are scaled down further, the probability of the occurrence of undesired short channel effects increases because of the short distance between the drain and source extension junctions
104
and
106
. Shallow drain and source extension junctions
104
and
106
are desired to minimize short channel is effects. Conventional thermal anneal processes are typically used in the prior art to activate dopant within the drain and source extension junctions
104
and
106
and within the drain and source contact junctions
108
and
112
. However, conventional thermal anneal processes which heat up the semiconductor substrate
102
to temperatures above about 900° Celsius cause thermal diffusion of the dopant within the drain and source extension junctions
104
and
106
to increase the depth of the drain and source extensions junctions
104
and
106
. Such increased depth of the drain and source extension junctions
104
and
106
enhances the probability of occurrence of the undesired short channel effects.
Thus, a mechanism is desired for activating dopant within the drain and source extension junctions
104
and
106
and within the drain and source contact junctions
108
and
112
without using a conventional thermal anneal process such that the drain and source extension junctions
104
and
106
remain shallow.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a field effect transistor is fabricated using dual laser thermal anneal processes for activating dopant within the extension and contact junctions of the field effect transistor to maintain the extension junctions to remain shallow.
In one embodiment of the present invention, in a method for fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on a portion of the active device area of the semiconductor substrate. First spacers are formed on sidewalls of the gate electrode and the gate dielectric. A contact dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain contact junction and a source contact junction. A contact laser thermal anneal with a contact laser fluence is performed to activate the contact dopant within the drain and source contact junctions. The first spacers on the sidewalls of the gate electrode and the gate dielectric are removed. An extension dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain extension junction and a source extension junction. An extension laser thermal anneal with an extension laser fluence is performed to activate the extension dopant within the drain and source extension junctions. The extension laser fluence of the extension laser thermal anneal is lower than the contact laser fluence of the contact laser thermal anneal. In this embodiment of the present invention, the extension junctions are formed after the contact junctions are formed.
In another embodiment of the present invention, the contact junctions are formed after the extension junctions are formed. In such an embodiment, in a method for fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on a portion of the active device area of the semiconductor substrate. An extension dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain extension junction and a source extension junction. An extension laser thermal anneal with an extension laser fluence is performed to activate the extension dopant within the drain and source extension junctions. Spacers are formed on sidewalls of the gate electrode and the gate dielectric. A contact dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain contact junction and a source contact junction. A contact laser thermal anneal with a contact laser fluence is performed to activate the contact dopant within the drain and source contact junctions. The steps for forming the contact junctions are performed after the steps for forming the extension junctions. The extension laser fluence of the extension laser thermal anneal is lower than the contact laser fluence of the contact laser thermal anneal.
In this manner, dual laser thermal anneal processes are performed for activating dopant within the contact and extension junctions of the field effect transistor such that a conventional thermal anneal process may not be used to activate dopant within such junctions. In such laser thermal anneal processes, a laser beam is directed toward the junctions for a short time duration of from about 1 nanosecond to about 10 nanoseconds.
With such laser thermal anneal processes, thermal diffusion of dopant within the extension junctions is minimized such that the extension junctions remain shallow to minimize shor

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