Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-18
2001-05-22
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S769000, C438S775000, C438S776000
Reexamination Certificate
active
06235590
ABSTRACT:
BACKGROUND
The present invention relates generally to the fabrication of integrated circuits and, in particular, to techniques for fabricating integrated circuits incorporating insulating layers such as gate oxides having different thicknesses.
Integrated circuits incorporating active elements such as metal-oxide-semiconductor (MOS) devices that are operated from multiple power supplies are being developed for various applications. Examples of such integrated circuits include dual gate CMOS circuits, peripheral circuits for non-volatile memory and circuits for driving liquid crystal flat panel displays, among others. Such circuits can include active elements that require a high supply voltage and other elements for which a low supply voltage is sufficient. In general, a high supply voltage may be required for high performance, high speed circuit elements, whereas a low supply voltage may be sufficient for low speed circuit elements on the same integrated circuit chip. For example, in some applications, a high supply voltage of 5 volts (V) can be used with a corresponding low supply voltage of 3.3 V.
Typically, MOS devices or other circuit elements that are to be operated from the high supply voltage are formed so that their gate oxide is relatively thick. Conversely, circuit elements that are to be operated from the low supply voltage are formed with a relatively thin gate oxide.
Although various techniques have been employed in the formation of the different oxide layers, a fabrication process which results in an integrated circuit having multiple gate oxides of different thicknesses as well as with improved electrical properties is desirable.
SUMMARY
In general, in one aspect, techniques are disclosed for fabricating an integrated circuit including devices having gate oxides with different thicknesses and a high nitrogen content. The techniques include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. The device with the thicker oxynitride layer is suitable for operation with a relatively high voltage, whereas the device with the thinner oxynitride layer is suitable for operation with a relatively low voltage.
In one implementation, a semiconductor substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides.
In another aspect, a method of fabricating an integrated circuit includes forming a first oxynitride layer on a surface of a substrate in an ambient comprising a nitrogen-containing gas at a pressure of a least 2.0 atmospheres. A portion of the first oxynitride layer is etched to expose a portion of the substrate surface. Subsequently, a second oxynitride is formed over the surface of the semiconductor in an ambient comprising a nitrogen-containing gas at a pressure of a least 2.0 atmospheres. The second oxynitride layer overlaps at least a portion of the first oxynitride to form a combined first insulating layer of a first thickness. A portion of the second oxynitride layer is formed on the semiconductor surface to form a second insulating layer having a second thickness less than the first thickness.
In yet a further aspect, an integrated circuit includes a substrate and first and second MOS devices formed on the substrate. Each MOS device includes drain and source regions formed in the substrate, an oxynitride gate having a nitrogen content in the range of about 0.2 to about 2.0 percent or a nitrogen content of at least 1.0×10
21
atoms/cm
3
, and a gate electrode formed on the oxynitride gate. The oxynitride gate of the first MOS device has a thickness greater than the thickness of the oxynitride gate of the second MOS device. For example, the thickness of the oxynitride gate of the first MOS device can be at least 1.25 times the thickness of the oxynitride gate of the second MOS device.
Various implementations include one or more of the following advantages. An integrated circuit having multiple gate oxides with different thicknesses can be fabricated. The different oxide thicknesses can be used, for example, in the fabrication of devices formed on a single wafer and requiring different operating voltages. Additionally, the invention allows gate oxides having different thicknesses and with a relatively high nitrogen content to be formed. The high nitrogen content can help prevent the diffusion of boron ions from the gate electrodes into the oxynitride gates, thereby improving device characteristics. For example, the high nitrogen concentration can give the devices a higher voltage tolerance and make them more resistant to breakdown. The device performance and lifetime of dual gate CMOS and circuits can, thereby be improved. Formation of the gate oxides in a high pressure furnace also can result in a more uniform distribution of nitrogen throughout the gate oxide which also improves performance of the devices.
Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings and the claims.
REFERENCES:
patent: 4240092 (1980-12-01), Kuo
patent: 5012315 (1991-04-01), Shur
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5444279 (1995-08-01), Lee
patent: 5464792 (1995-11-01), Tseng et al.
patent: 5497021 (1996-03-01), Tada
patent: 5498577 (1996-03-01), Fulford, Jr. et al.
patent: 5510278 (1996-04-01), Nguyen et al.
patent: 5516707 (1996-05-01), Loh et al.
patent: 5552332 (1996-09-01), Tseng et al.
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5610084 (1997-03-01), Solo de Zaldivar
patent: 5633523 (1997-05-01), Kato
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5716863 (1998-02-01), Arai
patent: 5750435 (1998-05-01), Pan
patent: 5783469 (1998-07-01), Gardner et al.
patent: 6037201 (2000-03-01), Tsai et al.
D. Lee et al., Reliability of Nitrided Si-SiO2Interfaces Formed by a New, Low Temperature, Remote-Plasma Process; J. Vac. Sci. Tech., pp. 1788-1793; Jul.-Aug., 1995.
C.G. Parker et al.; Ultrathin Oxide-Nitride Gate Dielectric MOSFET's, IEEE Electron Device Letters, vol. 19, No. 4, pp. 106-108; Apr., 1998.
IBM Technical Disclosure Bulletin, vol. 19, No. 3, Aug. 1976; Formation of Thick Si3N4or SixOyNzon SI Substrate by Anodnitridization; M.R. Poponiak et al.
GaSonics International; The Strategic Solution Advanced High Pressure Thermal Processing; http://www.gasonics.com/frames/prod/vhp.htm (Oct. 23, 1998).
Chisholm Michael F.
Daniel David W.
Pinello Dianne G.
Crane Sara
LSI Logic Corporation
LandOfFree
Fabrication of differential gate oxide thicknesses on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication of differential gate oxide thicknesses on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of differential gate oxide thicknesses on a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2467056