Fabrication of an EEPROM cell with SiGe source/drain regions

Details Fabrication of an EEPROM cell with SiGe source/drain regions Fabrication of an EEPROM cell with SiGe source/drain regions

2006-08-15

2006-08-15

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S202000

Reexamination Certificate

active

07091075

ABSTRACT:
An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

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patent: 2002/0098648 (2002-07-01), Ludwig et al.

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