Fabrication of a shallow doped junction having low sheet...

Details Fabrication of a shallow doped junction having low sheet... Fabrication of a shallow doped junction having low sheet...

1999-10-25

2001-05-22

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S306000, C438S528000, C438S529000

Reexamination Certificate

active

06235599

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuits, and more particularly, to a method for fabricating a shallow doped junction of an integrated circuit device having scaled down dimensions within a semiconductor substrate using a plurality of implantations to form a box-shaped implant profile such that the shallow doped junction has low sheet resistance.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
The present invention is described in reference to formation of a shallow doped junction with minimized sheet resistance as part of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the present invention may be used for any other type of integrated circuit device aside from just the example of a MOSFET where a shallow doped junction with minimized sheet resistance improves the performance of the integrated circuit device.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow doped junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be a polysilicon gate. A gate silicide
120
is formed on the polysilicon gate
118
for providing contact to the polysilicon gate
118
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the polysilicon gate
118
and the gate oxide
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the polysilicon gate
118
and the gate oxide
116
.
Referring to
FIG. 1
, as dimensions of the MOSFET
100
are scaled further down to tens of nanometers, the drain extension
104
and the source extension
106
are desired to be abrupt and shallow junctions to minimize short-channel effects of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, for enhancing the speed performance of the MOSFET
100
with scaled down dimensions, a low sheet resistance is desired for the junctions of the drain extension
104
and the source extension
106
.
Dopant within the drain extension
104
and the source extension
106
is activated typically using a RTA (Rapid Thermal Anneal) process, as known to one of ordinary skill in the art of integrated circuit fabrication. As dimensions of the MOSFET
100
are further scaled down, a lower temperature is desired for the RTA process because thermal diffusion of the dopant within the drain extension
104
and the source extension
106
causes the drain extension
104
and the source extension
106
to become less shallow. Thus, an amorphization implant is performed in the drain extension
104
and the source extension
106
before implantation of the dopant in the drain extension
104
and the source extension
106
. The amorphization implant lowers the melting temperature of the drain extension
104
and the source extension
106
such that activation of dopant within the drain extension
104
and the source extension
106
may be performed at a lower temperature.
Referring to
FIG. 2
, an amorphization implant profile
200
illustrates the concentration of an amorphizing implant species implanted into the semiconductor substrate
102
. Referring to
FIGS. 1 and 2
, the x-axis of the amorphization implant profile
200
indicates the depth of the semiconductor substrate
102
from a top surface
130
of the semiconductor substrate
102
. The y-axis of the amorphization implant profile
200
indicates the concentration of the amorphizing implant species implanted into a particular depth of the semiconductor substrate
102
.
The amorphization implant profile
200
is typically a Gaussian shape, as known to one of ordinary skill in the art of integrated circuit fabrication. For fabrication of shallow doped junctions for the drain extension
104
and the source extension
106
, the amorphizing implant species may be a heavy dopant species such as indium (In), arsenic (As), and antimony (Sb), for example, such that the amorphization implant profile
200
is relatively narrow.
For implantation of the relatively heavy dopant species, a high implantation energy may be used. However, with a high implantation energy, the amorphization implant profile
200
may be buried beneath the top surface
130
of the semiconductor substrate
102
, as illustrated in FIG.
2
. (Referring to
FIGS. 1 and 2
, the origin
201
of the x-axis in
FIG. 2
represents the top surface
130
of the semiconductor substrate
102
.) Referring to
FIG. 2
, the buried amorphization implant profile
200
is disadvantageous because an amorphization implant profile that is buried results in a doped junction with higher sheet resistance. In addition, the buried amorphization implant profile
200
has a first dislocation interface
202
and a second dislocation interface
204
where the concentration of the amorphizing implant species rapidly diminishes. Two such dislocation interfaces
202
and
204
may result in a doped junction with higher sheet resistance.
After implantation of the amorphizing implant species for forming a junction, dopant is implanted into the semiconductor substrate
102
. Referring to
FIG. 3
, a dopant implant profile
300
illustrates the concentration of a dopant implant species implanted into the semiconductor substrate
102
. Referring to
FIGS. 1 and 3
, the x-axis of the dopant implant profile
300
indicates the depth of the semiconductor substrate
102
from a top surface
130
of the semiconductor substrate
102
. The y-axis of the dopant implant profile
300
indicates the concentration of the dopant implant species implanted into a particular depth of the semiconductor substrate
102
. The dopant implant profile
300
is typically a Gaussian shape, as known to one of ordinary skill in the art of integrated circuit fabrication.
In the prior art, for minimizing resistance of a junction, a relatively high concentration of the dopant implant species may be implanted into the junction. However, in a RTA (Rapid Thermal Anneal) process for activating the dopant implant species within the junction, the activ

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