Fabrication of a planar MOSFET with raised source/drain by chemi

Details Fabrication of a planar MOSFET with raised source/drain by chemi Fabrication of a planar MOSFET with raised source/drain by chemi

1998-02-23

2000-10-17

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438300, 438595, 438591, H01L 21336, H01L 213205, H01L 214763

Patent

active

061331066

ABSTRACT:
A method of fabricating a MOSFET includes: depositing an oxide layer on the planarized substrate; forming a silicon nitride island above a gate region in the substrate; building an oxide sidewall about the nitride island; forming a source region and a drain region in the substrate; removing the silicon nitride island, thereby leaving a void over the gate region; forming a gate dielectric over the gate region in the void; filling the void and the areas over the source region and drain region; planarizing the upper surface of the structure by chemical mechanical polishing; depositing a metal layer on the upper surface of the structure; and metallizing the structure to form electrodes in electrical contact with the source region, the gate region, and the drain region.

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Kaufman et al., Chemical-Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects, J. Electrochem. Soc., vol. 138, No. 11, pp. 3460-3465, Nov. 1991.
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 3--The Submicron MOSFET, pp. 373, Jan. 1, 1995.

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