Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-03
2001-10-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000, C438S595000
Reexamination Certificate
active
06306710
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuits, and more particularly, to a method for fabricating a rectangular shaped spacer around a gate structure of a field effect transistor by forming a longer length toward the top of the gate structure.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is fabricated within a semiconductor substrate
102
which may be a silicon substrate.
FIG. 1
illustrates the cross-sectional view of the MOSFET as known to one of ordinary skill in the art of integrated circuits. The scaled down MOSFET having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow doped junctions to minimize shortchannel effects in the MOSFET having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
To further minimize short-channel effects in the MOSFET, a drain pocket
108
surrounds the drain extension
104
near the channel of the MOSFET, and a source pocket
110
surrounds the source extension
106
near the channel of the MOSFET, as known to one of ordinary skill in the art of integrated circuit fabrication. The drain extension
104
and the source extension
106
include an N-type dopant when the MOSFET is an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor). Alternatively, the drain extension
104
and the source extension
106
include a P-type dopant when the MOSFET is a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor). For minimizing short-channel effects within the MOSFET, the drain pocket
108
and the source pocket
110
are doped with a P-type dopant for an NMOSFET. Alternatively, the drain pocket
108
and the source pocket
110
are doped with an N-type dopant for a PMOSFET.
The MOSFET of
FIG. 1
further includes a gate dielectric
112
which may be comprised of silicon dioxide for the silicon substrate
102
and includes a gate structure
114
which may be a polysilicon gate. The MOSFET also includes a spacer
116
disposed on the sidewalls of the gate structure
114
and the gate dielectric
112
. The spacer
116
is comprised of a dielectric such as silicon dioxide for example.
The MOSFET of
FIG. 1
further includes a drain contact junction
118
such that a drain silicide may be formed therein for providing contact to the drain of the MOSFET and includes a source contact junction
120
such that a source silicide may be formed therein for providing contact to the source of the MOSFET. The drain contact junction
118
and the source contact junction
120
are fabricated as deeper junctions such that a relatively large size of the drain silicide and the source silicide respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET.
Referring to the cross-sectional view of the MOSFET of
FIG. 1
of the prior art, the gate structure
114
has a substantially rectangular shape, and the spacer
116
has a substantially triangular shape. During implantation of dopant for formation of the drain contact junction
118
and the source contact junction
120
, because the triangular shape of the spacer
116
results in a gradual diminishing of the thickness at the edges of the spacer
116
away from the gate structure
114
, the implantation energy used for implanting the dopant for the drain contact junction
118
and the source contact junction
120
is limited. Such a limitation in the implantation energy leads to limitation in the depth of the drain contact junction
118
and the source contact junction
120
. However, a large depth of the drain contact junction
118
and the source contact junction
120
is desired such that a large volume of silicide may be formed therein for providing low resistance contact to the drain and source of the MOSFET.
In addition, with such a limitation in the implantation energy, the drain contact junction
118
and the source contact junction
120
are not as abrupt and extend further under the dielectric spacer
116
resulting in undesired capacitance at the drain and source of the MOSFET which degrades the speed performance of the MOSFET. Furthermore, a high implantation energy would result in a deeper junction with a more gradual change in concentration of the implanted dopant. Such a gradual change in concentration of the implanted dopant would result in lower junction capacitance for the drain contact junction
118
and the source contact junction
120
for enhanced speed performance of the MOSFET.
Referring to
FIG. 2
, a drain silicide
122
is formed with the drain contact junction
118
for providing contact to the drain of the MOSFET, and a source silicide
124
is formed with the source contact junction
120
for providing contact to the source of the MOSFET. In addition, a gate silicide
126
is formed on the gate structure
114
for providing contact to the gate of the MOSFET. (Elements having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function.) In the MOSFET of
FIG. 2
of the prior art, because the spacer
116
is triangular in shape, the gate silicide
126
may contact the drain silicide
122
and the source silicide
124
according to the “bridging effect” as illustrated in
FIG. 2
to undesirably couple the gate, the drain, and the source of the MOSFET, as known to one of ordinary skill in the art of integrated circuit fabrication.
Because of these enumerated disadvantages of the triangular shaped spacer
116
of the prior art, a method for fabrication of a spacer having substantially a rectangular shape is desired. With a substantially rectangular shaped spacer, the implantation energy may be higher for implanting the dopant for formation of the drain contact junction
118
and the source contact junction
120
. With such a higher implantation energy, the drain contact junction
118
and the source contact junction
120
may be formed with deeper depth such that a larger volume of drain silicide and source silicide may be formed therein to provide low resistance contact to the drain and the source of the MOSFET.
In addition, with a rectangular spacer of the present invention, the drain contact junction
118
and the source contact junction
120
at the side toward the channel of the MOSFET are more abrupt junctions that extend less under the dielectric spacer
116
resulting in lower capacitance at the drain and source of the MOSFET to enhance the speed performance of the MOSFET. Furthermore, a high implantation energy results in deeper junctions with a more gradual change in concentration of the implanted dopant. Such a gradual change in concentration of the implanted dopant would result in lower junction capacitance for the drain contact junction
118
and the source contact junction
120
for enhanced speed performance of the MOSFET.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, the gate structure of the MOSFET of the present invention is formed to have a longer length toward the top of the gate structure such that a spacer having a substantially rectangular shape is formed at the sidewalls of the gate structure.
In one embodiment of the present invention, a method for fabricating a gate structure of a field effect transistor on a semiconductor substrate includes the step of depositing a layer of g
Bell Scott
Karlsson Olov
Liu Bill
Long Wei
Advanced Micro Devices , Inc.
Choi Monica H.
Lindsay Jr. Walter L.
Niebling John F.
LandOfFree
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