Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-07
2001-04-17
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000
Reexamination Certificate
active
06218246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a nonvolatile memory device, and more particularly to a fabrication method of triple polysilicon flash EEPROM arrays.
2. Description of the Conventional Art
FIGS. 1A through 1E
illustrate a conventional fabrication method of triple polysilicon flash EEPROM arrays, the method being disclosed in U.S. Pat. No. 5,712,179.
First, as shown in
FIG. 1A
, a first polysilicon strip
77
is formed in a first direction on a semiconductor substrate
31
having a source and a drain, and second polysilicon strips
56
,
55
,
53
,
51
,
58
are formed on the first polysilicon strip
77
in a second direction. A gate oxide layer
73
separates the first strip
77
from the substrate
31
, and a dielectric layer
103
separates the second strips from the first strip
77
, the first strip
77
later being separated into individual floating gates and the second polysilicon strips serving as control gates. Further, oxide strips
113
,
115
,
117
,
119
,
120
are positioned to cover top surfaces of the respective control gates
56
,
55
,
53
,
51
,
58
.
In
FIG. 1B
, temporary masking strips
305
,
309
are formed along one side of each of the control gate strips
53
,
55
, the first polysilicon strip
77
is partially etched, through a mask consisting of the masking strips
305
,
309
and the oxide strips
115
,
117
,
119
, to be separated into floating gates
301
,
303
,
305
and then the masking strips
305
,
309
are removed. Here, the masking strips
115
,
117
,
119
are preferably formed by depositing a layer of photoresist material over the structure, exposing it to optical radiation through a mask and then dissolving portions to leave the desired masking strips behind.
As shown in
FIG. 1C
, an oxide layer about 1500 Å thick is deposited by a chemical vapor deposition (CVD) process over the entire structure to completely fill the spaces between control gates
51
,
53
,
55
, and then the oxide layer is then anisotropically etched until substantially the surfaces of the oxide strips
115
,
117
,
119
are exposed. As a result, spacers
317
,
323
are formed along the vertical edges of the floating gates
301
,
303
, the control gates
51
,
53
,
55
are physically separated and electrically insulated by spacers
313
,
315
,
319
,
321
,
325
formed at side walls in the spaces between the rows and there are exposed portions
327
,
329
of an upper surface of the floating gates
55
,
53
, respectively.
Next, portions of the floating gate edges are removed by etching, using a mask formed of the spacers
315
,
319
, and the oxide strips
115
and
117
, as shown in
FIG. 1D. A
tunnel dielectric layer
331
is then grown over that newly exposed polysilicon edge.
In
FIG. 1E
, a third polysilicon layer is deposited over the structure with a thickness sufficient to fill in the spaces between the control gates
51
,
53
,
55
and then erase gates
335
,
337
,
339
are formed by photo-etching the third polysilicon layer. As a result, the erase gate
337
, for example, is coupled through the tunnel dielectric layer
331
with the floating gate
301
but is maintained a sufficient distance from the opposite floating gate
303
by the spacer
314
.
However, such method of fabricating the conventional flash EEPROM arrays has several problems. More specifically, the exposed side wall of the floating gate is not vertically formed due to the inclination of the side-wall spacer which is not right-angled after the etching process for exposing the edge of the floating gate, where the tunnel dielectric layer is to be formed, by using the mask formed of the controls gates and the side-wall spacer thereof. Therefore, the tunnel dielectric layer formed at such side wall vibrates the coupling of the control gates and the erasing properties of the erase gates are electrically unstable, which results in deterioration of the reliability of the semiconductor device.
In addition, since the insulation between the erase gate which erases the floating gate and the adjacent floating gate is accomplished through the corresponding side-wall spacer, the side-wall spacer should be thickly formed sufficient to have the complete insulation. Therefore, it is not suitable to memory cell arrays with large scale integration in which the distance between the control gates becomes smaller.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a fabrication method of triple polysilicon flash EEPROM arrays which obviates the problems and disadvantages due to the conventional art.
An object of the present invention is to provide a fabrication method of triple polysilicon flash EEPROM arrays that is suitable to memory cell arrays with large scale integration since each erase gate which erases one floating gate maintains sufficient distance with an opposite floating gate.
Also, another object of the present invention is to provide a fabrication method of triple polysilicon flash EEPROM arrays that uses portions of a dielectric layer as tunnel electric layers for thereby electrically stabilizing erasing properties for which electrons accumulated in floating gates are removed through the tunnel electric layers.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, according to an embodiment, there is provided a fabrication method of triple polysilicon flash EEPROM arrays, including forming a gate oxide layer on a semiconductor substrate having a source and a drain, forming a first polysilicon strip on said gate oxide layer in a first direction, forming a dielectric layer on said first polysilicon strip, forming second polysilicon strips on said dielectric layer in a second direction which is perpendicular to the first direction, forming oxide strips respectively on said second polysilicon strips, forming spacers at both side-walls of said oxide strips and said second polysilicon strips respectively formed thereon, forming a third polysilicon layer over the resultant structure, forming in the second direction masking strips which define erase gate regions on said third polysilicon layer, and forming individual erase gates and floating gates by sequentially etching the third polysilicon layer, the dielectric layer and the first polysilicon strip.
Further, to achieve the above objects, there is provided a fabrication method of triple polysilicon flash EEPROM arrays, according to another embodiment, which includes forming a gate oxide layer on a semiconductor substrate having a source and a drain, forming a first polysilicon strip on said gate oxide layer in a first direction, forming a dielectric layer on said first polysilicon strip, forming second polysilicon strips on said dielectric layer in a second direction which is perpendicular to the first direction, forming oxide strips respectively on said second polysilicon strips, forming spacers at both side-walls of said oxide strips and said second polysilicon strips respectively formed thereon, removing portions of said oxide strips and the spacers formed at one side of the side-walls of said oxide strips by a photo-etching process, forming a third polysilicon layer over the resultant structure, forming in the second direction masking strips which define erase gate regions on said third polysilicon layer, and forming individual erase gates and floating gates by sequentially etching the third polysilicon layer, the dielectric layer and the first polysilicon strip.
REFERENCES:
patent: 5686332 (1997-11-01), Hong
patent: 5712179 (1998-01-01), Yuan
patent: 5838039 (1998-11-01), Sato et al.
patent: 5874759 (1999-02-01), Park
Chaudhari Chandra
Chen Jack
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
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