Fabrication method of trenched power MOSFET with low gate...

Details Fabrication method of trenched power MOSFET with low gate... Fabrication method of trenched power MOSFET with low gate...

2008-11-06

2009-10-27

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C257SE21655

Reexamination Certificate

active

07608511

ABSTRACT:
A fabrication method of a trenched power MOSFET with low gate impedance is provided. The fabrication method comprising the steps of: forming a plurality of trenches in an epitaxial layer; forming a gate oxide layer on the epitaxial layer; forming a plurality of polysilicon gates in the trenches; implanting dopants with a first conductivity type into the epitaxial layer; driving-in the dopants in an oxygen-free environment to form a body; implanting dopants with a second conductivity type into the body; driving-in the dopants with the second conductivity type in an oxygen-free environment to form a plurality of source regions; forming self alignment silicide on the polysilicon gates by using the gate oxide layer as a mask; depositing a dielectric layer on the epitaxial layer and forming a window therein exposing the source regions; and forming a heavily doped region of the first conductivity type in the body beneath the window.

REFERENCES:
patent: 6489204 (2002-12-01), Tsui

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