Fabrication method of the post structure of the cell for high de

Details Fabrication method of the post structure of the cell for high de Fabrication method of the post structure of the cell for high de

1996-06-21

1997-09-16

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 2170

Patent

active

056680368

ABSTRACT:
A method is disclosed to form memory cell structures for DRAMs in which the capacitor nodes are formed in the shape of posts that fit in an area no larger than that which is over the active regions of the semiconductor substrate. Hence, the posts are suitable to accommodate the area that is appropriate for any one of the very high density DRAMs up to and including 1 G-bit. Furthermore, one less mask is used to form the node electrode in comparison with prior art. The interior of said post structure constitutes one electrode and the exterior wall the other, while a thin dielectric separates the two polysilicon plates of the capacitor. It is shown that said post structures perform the multi-function of providing a good support during the planarization process. Optional pillars may be formed at judiciously chosen locations in the cell to provide additional storage nodes and/or more uniform support structures to more readily facilitate chemical-mechanical polishing (CMP) of the substrate surface. In an alternate approach for increasing the storage capacity of capacitors in DRAMs, a branched-post structure is used. It is predicted that cells with four branches can allow the manufacture of 1 G-bit DRAMs.

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S. Wolf, "Silicon Processing for the VLSI Era-vol. 2" Lattice Press, Sunset Beach CA, 1990, pp. 598, 609.
"Chemical-Mechanical Polishing: A New Focus on Consumables" by P. Singer, Pubin Semiconductor-Internatioanl, Feb., 1994 pp. 48-52.

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