Fabrication method of single electron tunneling device

Details Fabrication method of single electron tunneling device Fabrication method of single electron tunneling device

2000-11-17

2001-07-31

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S927000, C438S962000, C438S979000

Reexamination Certificate

active

06268273

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a single electron tunneling (SET) device, and more particularly, to a method of fabricating a SET device using the electromigration induction effect.
2. Description of the Related Art
SET devices, which apply the movement of single electrons between two electrodes, are applied to sensors, diodes, transistors and others. For example, in a SET transistor, as shown in
FIG. 1
, a drain electrode
2
and a source electrode
3
are installed opposite to each other at an interval of several hundreds of nanometer on an insulating substrate
1
. A plurality of nano-sized quantum dots
4
exist on an electron transferring area between the drain and source electrodes
2
and
3
, and a gate electrode
5
is located near the electron transferring area. In a transistor having such a structure, when the gate electrode
5
is electrically in a floating state (that is, 0V), the transistor acts as a diode.
In a transistor having such a structure, a threshold voltage Vt due to a coulomb gap where the movement of electrons starts exists between the drain and source electrodes
2
and
3
. Accordingly, as shown in
FIG. 2
, when a gate voltage Vg is 0V, that is, when an SET transistor acts as a diode, the movement of electrons does not start until a voltage V
DS
, which is greater than the threshold voltage Vt, is applied between the drain and source electrodes
2
and
3
. At a voltage that is equal to or less than the threshold voltage, a current I
DS
is theoretically 0 Å. At a voltage that is greater than the threshold voltage, a voltage-to-current has a linear characteristic.
A coulomb gap is controlled by a gate voltage Vg, as shown in FIG.
3
. If a gate voltage is 0V, a coulomb gap given to a device itself is maintained, as described referring to FIG.
2
. When a gate voltage increases to Vg
1
or Vg
2
within a predetermined range, a coulomb gap is narrowed. Thus, a threshold voltage at which a transistor operates is reduced.
The above-described SET device, which is several hundreds of nanometers in size, is manufactured by a self assembled monolayer (SAM) method or a nanolithography method. An SET device manufactured by the SAM method is suitable for a large scale integration (LSI) structure, but has a high material dependency. Thus, this SET device is limited in its application. An SET device manufactured by nanolithography has no material dependency, but formation of nano-sized quantum dots is difficult because of the fine pattern formation limit of a lithographic method. Therefore, it is actually impossible that this SET device is applied to LSI structures.
Quantum dots can be formed by electron beam ions on the basis of a method which overcomes the aforementioned limits of the SAM method and the nanolithography method. However, this is not suitable for mass production.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a method of fabricating a single electron tunneling (SET) device, by which the SET device can be mass-produced.
Another objective of the present invention is to provide a method of fabricating a single electron tunneling (SET) device, which is suitable for large scale integration (LSI) structures.
To achieve the above objectives, the present invention provides a method of fabricating a single electron tunneling (SET) device, the method including: forming a source electrode and a drain electrode a predetermined distance apart from each other on an insulating substrate; forming a metal layer having a thickness on the order of nanometers to maintain a predetermined interval between the source and drain electrodes; and forming quantum dots between the source and drain electrodes due to the movement of metal atoms/ions within the metal layer caused by applying a predetermined voltage to the source and drain electrodes.


REFERENCES:
patent: 5589692 (1996-12-01), Reed
patent: 5763933 (1998-06-01), White

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