Fabrication method of semiconductor device with capacitor

Details Fabrication method of semiconductor device with capacitor Fabrication method of semiconductor device with capacitor

2002-04-25

2003-09-23

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

06624020

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device. Particularly, the present invention relates to a semiconductor device having a capacitor such as a DRAM (Dynamic Random Access Memory), and a method of fabricating such a semiconductor device.
2. Description of the Background Art
Reflecting the remarkable development of semiconductor devices in recent years, there is a great diversity in the category of semiconductor devices in accordance with their application and function. There are a plurality of methods in fabricating a semiconductor device of the same type. It is desirable to select an appropriate fabrication method matching their application and function. For example, there are various formation methods for a capacitor indispensable in a DRAM. It has become critical to select the optimum method of forming a capacitor according to the application and function.
A DRAM is generally constituted by a memory cell array which is the storage region to store various storage information, and a logic circuit controlling memory cells in the memory cell array for data input/output with an external source. A memory cell array is formed of a plurality of memory cells in a matrix, storing unitary storage information. In a general DRAM, a memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected to the MOS transistor to store information. Such a memory cell is well known as a one-transistor one-capacitor type memory cell.
FIG. 13
is a schematic sectional view of a one-transistor one-capacitor memory cell in a DRAM to describe a structure thereof. Referring to
FIG. 13
, a plurality of MOS transistors
120
are formed at a main surface of a semiconductor substrate
101
electrically isolated by an isolation film
102
which is an element isolation region. MOS transistor
120
includes a source/drain diffusion layer
121
at an active region of the main surface of semiconductor substrate
101
.
Three major layers are deposited on the main surface of semiconductor substrate
101
. As shown in
FIG. 13
, the gate electrode layer and the like of MOS transistor
120
are formed at the lower most layer A of the three layers. At the intermediate layer B, a capacitor
110
and the like are formed. At the top most layer C, a metal line
133
and the like connecting memory cells with each other are formed.
First, the lower most layer A will be described. The main surface of semiconductor substrate
101
is covered by a thin gate oxide film
122
. A gate electrode layer
123
is formed at a predetermined position above gate oxide film
122
. Although not depicted, gate electrode layer
123
is constituted by a floating gate formed of a polycrystalline silicon layer into which impurities are introduced (referred to as “doped polysilicon layer” hereinafter), and a control gate formed of a tungsten silicide (WSi
2
) layer.
A silicon nitride film
125
is formed on gate electrode layer
123
. A sidewall
124
formed of a silicon oxide film is provided at the sidewall of gate electrode layer
123
. Regarding the pair of source/drain diffusion layers
121
, a pad layer
131
a
is connected to one of source/drain diffusion layers
121
and each bit line
131
b
is connected to the other of source/drain diffusion layers
121
. An interlayer insulating film
103
is formed all over the main surface of semiconductor substrate
101
so as to fill the gap between pad layer
131
a
and bit line
131
b
and cover the surface of MOS transistor
120
.
The intermediate layer B will be described here. On interlayer insulating film
103
of the above-described lower most layer A, a silicon nitride film
104
that is a stopper film for the formation of a trench used to form a capacitor, and a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) film
105
which is a spacer film are formed at the intermediate layer B. A trench for formation of a storage node is formed at a predetermined position in silicon nitride film
104
and BPTEOS film
105
so as to arrive at interlayer insulating film
103
.
Capacitor
110
includes a storage node
111
which is a lower electrode, a capacitor dielectric layer
112
, and a cell plate
113
which is an upper electrode. Storage node
111
is formed along the sidewall and bottom of the aforementioned trench. Storage node
111
is electrically connected to pad layer
131
a
at its bottom to be further connected to source/drain diffusion layer
121
of MOS transistor
120
via pad layer
131
a.
Cell plate
113
is formed facing storage node
111
with capacitor dielectric layer
112
therebetween.
At the top most layer C, interlayer insulating films
107
and
108
are formed so as to cover BPTEOS film
105
and capacitor
110
of the above-described intermediate layer B. A metal line
133
connecting metal cells with each other is formed in interlayer insulating films
107
and
108
. Metal line
133
is electrically connected to source/drain diffusion layer
121
of MOS transistor
120
through a bit line
132
passing through intermediate layer B and a bit line
131
b
passing through lower most layer A.
A method of forming a DRAM capacitor of the foregoing structure will be described here. MOS transistor
120
, pad layer
131
a,
bit line
131
b
and the like are formed in advance at the main surface of semiconductor substrate
101
in which isolation film
102
is formed. Lower most layer A is formed by providing an interlayer insulating film
103
so as to cover the surface thereof.
In the formation of a capacitor, first a silicon nitride film
104
is formed all over the main surface of interlayer insulating film
103
corresponding to the lower most layer A. Then, BPTEOS film
105
is formed thereon. A storage node formation trench is provided in silicon nitride film
104
and BPTEOS film
105
by conventional photolithography and etching techniques. Doped polysilicon layer
111
is formed so as to cover the sidewall and bottom of this storage node formation trench. Then, the surface of doped polysilicon layer
111
is roughened. This roughening process is applied to improve the capacitance of the capacitor.
The trench is filled with a photoresist. Using this photoresist as a mask, anisotropic etching is applied all over (etchback) until the surface of at least BPTEOS film
105
is exposed. When storage node
111
is formed by this etchback process, the photoresist in the trench is removed. Then, the native oxide film is removed by buffer hydrofluoric acid (BHF) using a mixture of hydrofluoric acid and ammonium fluoride. Following this removal, capacitor dielectric layer
112
and cell plate
113
are formed. Thus, a capacitor
110
is completed.
By forming a capacitor
110
using a silicon nitride film
104
which is a stopper film and a BPTEOS film
105
which is a spacer film, a cylinder type capacitor of a large capacitance can be obtained.
However, a semiconductor device fabricated by the above-described method had the problem that the reliability is low. This issue will be described in detail hereinafter.
The aforementioned roughening process is effected by growing crystal grains of silicon on the underlying layer which is the doped polysilicon layer. Conventionally, an etching process by BHF is carried out after the roughening process for the removal of the native oxide film. This BHF includes a mixture of hydrofluoric acid and ammonium fluoride. Silicon is etched by the ammonium fluoride.
The crystal grains readily fall off from the underlying layer. There is a possibility that these crystal grains will adhere onto the top surface of the BPTEOS film. The reattaching crystal grains may cause shorting between adjacent storage nodes, resulting in degradation of the reliability of the semiconductor device.
In etching back the doped polysilicon layer formed at the top face of the BPTEOS film, anisotropic etching was conventionally employed. This anisotropic etching generates residues along the sidewall of the pattern by the a

Affiliated with

Also associated with

Rating

Fabrication method of semiconductor device with capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication method of semiconductor device with capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method of semiconductor device with capacitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3054159