Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2010-11-02
2011-12-20
Ahmadi, Mohsen (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S243000, C438S270000, C438S589000, C257SE21382, C257SE21384, C257SE21396, C257SE21419
Reexamination Certificate
active
08080457
ABSTRACT:
A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. Then, a spacer is formed on the dielectric layer covering the sidewall of the gate trench. Thereafter, a plug structure is formed in the space at the bottom of the gate trench, which is defined by the spacer. Then, a portion of the spacer is removed with the dielectric structure and the plug structure as an etching mask. Thereafter, a portion of the dielectric layer is removed with the remained spacer as an etching mask to expose the inner surface of the upper portion of the gate trench. Afterward, with the remained spacer being kept, a gate dielectric layer is formed on the inner surface of the upper portion of the gate trench, and then a polysilicon gate is filled into the upper portion of the gate trench.
REFERENCES:
patent: 6251730 (2001-06-01), Luo
patent: 6621107 (2003-09-01), Blanchard et al.
patent: 7923776 (2011-04-01), Yilmaz et al.
patent: 7994001 (2011-08-01), Hsu et al.
Ahmadi Mohsen
Great Power Semiconductor Corp.
Jianq Chyun IP Office
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