Fabrication method of a self-aligned contact window

Details Fabrication method of a self-aligned contact window Fabrication method of a self-aligned contact window

1999-06-19

2001-06-12

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S639000, C438S595000

Reexamination Certificate

active

06245625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device. More particularly, the present invention relates to a fabrication of a self-aligned contact window (SAC).
2. Description of the Related Art
In the conventional fabrication method of a self-aligned contact window, a silicon oxide layer is formed between a silicon nitride spacer and a word line gate. During the etching process to form a self-aligned contact window, if a misalignment occurs in process of defining the self-aligned contact window, formation of a trench in the silicon oxide layer located between the silicon nitride spacer and the word line gate may result.
FIG. 1
is a schematic, cross-sectional view of a self-aligned contact window according to the prior art. As shown in
FIG. 1
, a word line gate
110
, comprising a gate oxide layer
102
, a polysilicon layer
104
, a tungsten silicide layer
106
and a silicon nitride roof layer
108
, is formed on a semiconductor substrate
100
. A silicon oxide layer
114
is further formed between a silicon nitride spacer
112
and the word line gate
110
to improve the adhesion between the silicon nitride spacer
112
and the word line gate
110
. A silicon oxide layer
116
is deposited to cover the word line gate
110
and to insulate the word line gate
110
from the bit line formed in a latter part of the process. After this, a silicon oxide layer
116
is defined to from a self-aligned contact window
118
. However, if the silicon oxide layer
114
formed between the silicon nitride spacer
112
and the word line gate
110
is too thick, etching is likely to occur along the silicon oxide layer so that a trench
120
is formed during the SAC
118
etching. More seriously, the tungsten silicide layer
106
is exposed. Furthermore, before the bit line is formed, a wet chemical wash with, for example, RCA solution is conducted and results in an additional portion of the silicon oxide layer being rinsed off during the wash, which enhances the possibility of exposing the tungsten silicide layer
106
. As a result, a bit line formed in a latter part of the process is electrically connected to the source/drain region
114
, leading to an electrical connection between the word line gate
110
and the bit line, giving rise to a short circuit.
A conventional approach in resolving the above problem is to reduce the thickness of the buffer silicon oxide layer
114
. The possibility of forming the trench
120
due to etching of the silicon oxide layer
114
in between the silicon nitride spacer
112
and the world line gate
104
is thereby reduced. However, another problem may arise with the conventional approach. Since the thickness of the silicon oxide layer
114
is reduced, the distance between the silicon nitride spacer
112
and the substrate
100
is decreased, inducing stresses between the silicon nitride spacer
112
and the silicon oxide layer
114
or between the silicon nitride spacer
112
and the substrate
100
. As a result, a dislocation may occur in the substrate
100
, which has a single crystal structure.
Another approach to mitigate the problem occurred in the conventional practice is to induce a reaction on the exposed surfaces of the silicon, polysilicon and tungsten silicide to form silicon oxide via a thermal oxidation in order to prevent the stress issue with the silicon nitride spacer. A short circuit due to an electrical connection between the word line gate
110
and the bit line is also prevented. Silicon nitride, however, does not react to form silicon oxide. In addition, a thermal oxidation treatment further subjects the device to an addition thermal cycle, which strongly affects the characteristics of the device and easily induces a dislocation in the substrate
100
, which has a single crystal structure.
SUMMARY OF THE INVENTION
The current invention provides a fabrication method of a self-aligned contact window in which a substrate, with a gate and a lightly doped region already formed on the substrate, comprises a first dielectric layer with a thickness of 300-500 Å. The upper surface of the first dielectric layer is lower than the upper surface of the gate, which completely reveals the roof layer of the gate. A spacer is further formed on the exposed sidewall of the gate. Using the gate and the spacer as masks, the first dielectric layer is etched until the lightly doped region is partially exposed. Still using the gate and the spacer as masks, a heavily doped region is formed in the lightly doped region and the substrate. Consequently, a second dielectric layer is formed covering the gate. Using the spacer of the gate and the roof layer of the gate as masks, the second dielectric layer is then defined to form a self-aligned contact window.
By insulating the silicon nitride spacer from the substrate with a silicon oxide layer, the silicon nitride spacer is not in direct contact with the substrate. As a result, a dislocation in the substrate resulting from a stress caused by direct contact of the silicon nitride spacer with the substrate, which commonly occurs in the conventional practice, is prevented.
Furthermore, the need to form a silicon oxide layer between the spacer and the gate is eliminated in the present invention. As a result, a trench cannot be formed along the silicon oxide layer during a SAC etching. A short circuit resulting from an electrical connection between the bit line and the word line gate is also prevented.
In addition, according to the current invention, the silicon nitride spacer is not in direct contact with the substrate; therefore, the use of thermal oxidation to form a silicon oxide layer, as in the conventional practice, can be avoided. As a result, the problem of a dislocation in the substrate due to a thermal treatment is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5817562 (1998-10-01), Chang et al.
patent: 5994192 (1999-11-01), Chen
patent: 6004853 (1999-12-01), Yang et al.
patent: 6010954 (2000-01-01), Ho et al.
patent: 6057196 (2000-05-01), Gau
patent: 6083828 (2000-07-01), Lin et al.

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