Fabrication method of a gate junction conductive structure

Details Fabrication method of a gate junction conductive structure Fabrication method of a gate junction conductive structure

1999-07-19

2001-09-18

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000, C438S682000

Reexamination Certificate

active

06291301

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device. More particularly, the present invention relates to a fabrication method of a gate junction conductive structure.
2. Description of the Related Art
When the density of an integrated circuit is further increased, the device dimensions such as the line width, the contact surface area and the junction depth are continuously being reduced to a deep submicron level. To effectively ensure the functional integrity of the device, to lower the resistance and to minimize the RC delay resulted from a reduced resistance and capacitance, a metal silicide is commonly used in the manufacturing of a gate for lowering the contact resistance of a polysilicon gate. Since the formation of a metal silicide eliminates the needs of a photolithography process, the process is also being referred as a self-aligned silicide (salicide) process. Common examples of a self-aligned silicide include titanium silicide (TiSi
x
) and cobalt silicide (CoSi
x
).
In the conventional self-aligned silicide process, using titanium silicide as an example, a transistor device and the device isolation region are first completed. The transistor comprises a polysilicon gate and a source/drain region. A layer of titanium is deposited on the entire substrate, and thermal treatment is then conducted to form a silicide layer. Silicide is formed at the elevated temperature where titanium is in contact and reacted with the silicon of the gate and the surface of the source/drain region. The unreacted metal is removed, leaving only the titanium silicide layer on the surface of the gate and the source/drain region. After that, an annealing procedure is conducted to enhance the quality of the titanium silicide layer.
As the dimensions of a polysilicon gate are gradually being reduced, a narrow line effect often occurs. A narrow line effect may result from too small a gate dimension, less than 0.18 &mgr;m, such that the contact stress between the metal silicide and the polysilicon is too high during the formation of the metal silicide on the polysilicon gate. A narrow line effect may also result from too little a nucleation site, thereby reducing the quality of the metal silicide thin film, leading to an increase in the sheet resistance and affecting the operational efficiency of the gate.
To improve the quality of a metal silicide layer, a higher temperature by means of a rapid thermal processing (RTP) is used. A higher temperature, however, affects the characteristic of a shallow junction device. Furthermore, the issue of filament, which may lead to a shortage at the gate and at the source/drain region and resulted in a damage to the device, easily occurs between the gate and the source/drain region in the self-aligned silicide process.
SUMMARY OF THE INVENTION
This invention provides a fabrication method of a gate junction conductive structure in which the area of the gate junction surface for the formation of a metal silicide layer is increased. As a result, the occurrence of the narrow line effect is prevented. The sheet resistance and the temperature for the thermal treatment are also lower, thereby reducing the negative effect on the shallow junction device.
The present invention provides a fabrication method of a gate junction conductive structure in which a substrate is provided and the substrate comprises at least a gate. The gate comprises an exposed silicon conductive layer, for example a polysilicon layer. The sidewall of the silicon conductive layer comprises a spacer, and at both sides of the gate, a source/drain region is formed in the substrate. An insulation layer is further formed covering the silicon substrate and the gate. A portion of the insulation layer is removed until the silicon conductive layer is exposed. A selective silicon deposition process, in which silicon only deposits on the silicon type materials, is conducted to form a silicon layer on the silicon conductive layer. Since the area of the silicon layer is slightly greater than that of the silicon conductive layer, the occurrence of a narrow line effect is prevented. Using the silicon layer as a mask, a portion of the insulation layer is further removed to expose the source/drain region. A second spacer is also formed on the existing spacer over the spacer of the gate and covers portions of the source/drain region. A self-aligned metal silicide process is then conducted to convert the silicon layer and the surface of the source/drain region to a layer of metal silicide.
Since the silicon layer formed according to the present invention comprises a greater area, the gate junction surface for forming the metal silicide layer is also increased. With a greater gate junction surface, not only the narrow line effect can be prevented, the temperature required for the thermal treatment in forming the metal silicide layer is also lower. Thus, the metal silicide formed has a lower sheet resistance and is more stable. Furthermore, according to the present invention, a second spacer is formed in addition to the original spacer to increase the thickness of the spacer. In addition, the temperature used in forming the metal silicide layer is lower. Therefore, the issue of filament between the gate and the source/drain region can be prevented and the electric field between the two components is indirectly lowered. As a result, the stability of the device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5045916 (1991-09-01), Vor et al.
patent: 5953614 (1999-09-01), Liu et al.
patent: 6015753 (2000-01-01), Lin et al.
patent: 6025254 (2000-02-01), Doyle et al.

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