Fabrication method of a dual-gate CMOSFET

Details Fabrication method of a dual-gate CMOSFET Fabrication method of a dual-gate CMOSFET

2000-03-13

2002-07-02

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S232000, C438S305000

Reexamination Certificate

active

06413810

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a high-speed dual-gate CMOSFET with high reliability.
2. Description of the Related Art
Recently, the fineness of the gate length of a MOSFET has been reduced to approximately 0.1 &mgr;m, as large-scale integrated circuits have become highly integrated. The finer gate length increases a transconductance (gm), resulting in a shorter delay time. Consequently, a MOSFET can operate at a higher speed.
In order to make a normally operating MOSFET having a fine gate, and in particular, a PMOSFET, it is important to suppress a short channel effect. For a PMOSFET having a fine gate, a surface channel (SC) type MOSFET including a gate electrode of P
+
polysilicon has become common, rather than a buried channel (BC) type MOSFET including a gate electrode of N
+
polysilicon, which was widely used conventionally.
A CMOSFET in which an N
+
polysilicon gate electrode is used an NMOSFET while a P
+
polysilicon gate electrode is used in PMOSFET is called a dual-gate CMOSFET.
An exemplary fabrication method of the dual-gate CMOSFET is described by K. F. Lee et al., in “IEDM Tech. Dig.” (1993), p. 131.
FIGS. 1A-1E
and
2
F-
2
H are diagrams schematically showing processes of this method. In
FIGS. 1A-1E
and
2
F-
2
H the NMOSFET is shown the left side while the PMOSFET is shown on the right side.
In accordance with this method, a recessed LOCOS (Local Oxidation of Silicon) film
122
of 750 nm thickness is formed on a silicon substrate
121
using a known technique. A P well
123
a
and an N well
123
b
are then formed using a high-energy ion implantation apparatus. In this example, the P well
123
a
is formed by implanting boron (B) of 1≧10
13
cm
−2
with 400 keV, and the N well
123
b
is formed by implanting phosphorus (P) of 1≧10
13
cm
−2
with 900 keV (FIG.
1
A).
Next, a resist pattern is formed (not shown), to be used as a mask for defining an ion implantation region. Using the resist pattern as the mask, punchthrough suppression implantation for suppressing the short channel effect, and channel implantation for controlling a threshold voltage are performed by ion, implantation, only in regions
124
a
,
124
b
that are to be positioned under gates.
For example, the punchthrough suppression-implantation and the channel implantation for the P well are performed in the region
124
a
by implanting boron of 4≧10
12
cm
−2
with 45 keV and boron fluoride (BF
2
) of 1≧10
13
cm
−2
with 90 keV.
On the other hand, the punchthrough suppression implantation and channel implantation for the N well are performed in the region
124
b
by implanting phosphorus (P) of 4≧10
12
cm
−2
with 120 keV and arsenic (As) of 1≧10
13
cm
−2
with 100 keV (FIG.
1
B).
A gate oxidation film
125
is then formed with a thickness of 4 nm, in a furnace at 800° C. On the gate oxidation film
125
, a polysilicon film
126
having a thickness of 200 nm and a silicon nitride film
127
having a thickness of 100 nm are deposited by LPCVD, and thereafter a resist pattern (not shown) to be used as a mask for patterning gate electrodes is formed.
Using the resist pattern as the mask, unnecessary portions of the polysilicon film
126
and the silicon nitride film
127
are etched away, thus forming polysilicon gate electrodes
126
, each having a gate length of about 0.1 &mgr;m (FIG.
1
C).
Next, a resist is formed (not shown), for preventing ion implantation into undesired portions. Using the thus formed resist pattern as the mask, As of 5×10
14
cm
−2
is introduced by ion implantation at 10 keV to form a shallow junction source and drain of the NMOSFET (shallow junction S/D)
128
a
(FIG.
1
D).
After an SiO
2
film having a thickness of 50 nm is deposited using TEOS by CVD, the SiO
2
film is etched back by reactive ion etching (RIE) to form first side walls
129
. A resist pattern (not shown) for preventing ion implantation into undesired portions is then formed. Using the resist pattern, BF
2
of 1≧10
15
cm
−2
is introduced with 10 keV to form a shallow junction source and drain
128
b
of the PMOSFET (FIG.
1
E).
Next, SiO
2
film having a thickness of 200 nm is deposited again using TEOS by CVD, following which the SiO
2
film is etched back by reactive ion etching (RIE), to form second side walls
130
(FIG.
2
F).
Then, deep junction S/Ds
131
a
,
131
b
are formed by ion implantation. The deep junction source and drain
131
a
of the NMOSFET are formed by implanting As of about 5≧10
15
cm
−2
with 20 keV while the deep junction source and drain
131
b
of the PMOSFET are formed by implanting BF
2
of about 5≧10
15
cm
−2
with 10 keV.
Simultaneously, impurities such as As or BF
2
, are also introduced into the polysilicon gate electrodes
126
. More specifically, As is introduced into the gate electrode of the NMOSFET so that an N
+
polysilicon gate electrode
126
a
is obtained. On the other hand, BF
2
is introduced into the gate electrode of the PMOSFET so that a P
+
polysilicon gate electrode
126
b
is obtained (FIG.
2
G).
Annealing is then performed for 10 seconds at 1050° C. by a rapid annealing apparatus (RTA) and then drive-in is performed in a typical electric furnace at 800° C. for 20 minutes, thus producing a dual-gate CMOSFET having a fine gate length (FIG.
2
H).
As mentioned above, the CMOSFET which includes an NMOSFET having an N
+
polysilicon gate electrode, and a PMOSFET having a P
+
polysilicon gate electrode is fabricated by introducing the same impurities into the gate electrodes as those introduced into the source and the drains during the S/D ion implantation. The CMOSFET thus fabricated can withstand the short channel effect, operate at a high speed and have a high reliability.
The thus fabricated CMOSFET, however, has a problem where the threshold voltage may vary because of penetration of boron (B) included in P
+
polysilicon, into the channel region, through the gate oxidation film during the annealing process.
In order to avoid penetration of boron (B), the following three methods can be considered.
(1) Only boron is used as the impurity introduced into the source and the drain.
(2) The annealing process is performed at a lower temperature.
(3) A film to which nitrogen (N) is added is used as the gate oxidation film.
Regarding method (1), the penetration of boron (B) frequently occurs when boron fluoride (BF
2
) is implanted into the gate electrode. In other words, when just boron is implanted, penetration of boron does not occur as long as the temperature is kept relatively low or the concentration of boron is kept low. Therefore, it can be considered that boron is introduced by boron implantation. In this case, however, the junction of the S/D becomes deeper when boron is implanted into both the source and the drain simultaneously because boron is a light element. This makes the resultant MOSFET inappropriate for a MOSFET having a fine gate length.
Implantation with an energy level of 1 keV or less or implantation using decaborane (B
10
H
16
), which is a heavy element including no fluorine (F), has recently attracted attention. Such implantation, however, requires a special ion implantation apparatus, thus increasing the fabrication cost. In addition, it is difficult to immediately apply such implantation to the fabrication process because the development of such implantation technology is relatively recent.
Regarding method (2), even if boron fluoride (BF
2
) is used, the penetration of boron through the gate oxidation film does not cause fluctuation of the threshold voltage, as long as the annealing process is performed at a relatively low temperature and for a short time period. According to the experiments by the inventors of the present invention, in a case of the gate oxidation film having a thickness of 35 angstroms, the threshold voltage fluctuated when the annealing process was performed at 1050° C. for 10 se

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