Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-27
2001-06-19
Bowers, Charles (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S595000, C438S421000, C438S619000
Reexamination Certificate
active
06248622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for an ultra short channel device having a self-aligned landing pad.
2. Description of the Related Art
As the design rule of a semiconductor device is gradually reduced, the control of the critical dimension in a photolithography process, however, is hindered by the limitations of the light resolution and the depth of focus (DOF). This hindrance seriously affects the pursuit of a reduced memory cell area. Even when using an improved technique, such as the phase shift mask (PSM), the photoresist is still unable to provide a reproducible definition.
The conventional approach to reducing the critical dimension usually requires employment of a more complicated mask, for example, a phase shifting mask (PSM), and to conduct a special exposure technique, for example, an off-axial illumination. The purpose of reducing the critical dimension is achieved with the above approach; the manufacturing cost of an integrated circuit, however, is also increases significantly.
Although photolithography is one of the major techniques leading the development of a semiconductor device, it is also a major contribution to the manufacturing cost of the semiconductor. It is therefore desirable to employ less technically demanding photolithography techniques to form a small channel length and a device with a smaller dimension. Both the cost of production and the technical demands can be lowered while the operating speed of the device is improved.
Furthermore, due to the increase of the integration of a dynamic random access memory (DRAM) device, the dimensions of the memory cell and the area occupied by the DRAM capacitor are being reduced. Lowering the device dimension, however, would lower the capacitance. For a highly integrated DRAM device, a three dimensional capacitor is needed to maintain its capacitance at an acceptable value. As a result, a stacked capacitor, a trench-stacked capacitor or a crown-shaped capacitor is used to provide a large capacitor area and to lower the interference between the DRAM memory cells. As the complexity of the capacitor structure continues to increase, the height of the capacitor also increases. A capacitance-over-bit line is therefore normally used for the design of a storage node to avoid the limitation of space in the design of a capacitor.
FIGS. 1A
to
1
C are schematic, cross-sectional views showing the manufacturing of a semiconductor device according to the prior art.
Referring to
FIG. 1A
, according to the conventional fabrication method of a semiconductor device, a shallow trench isolation structure
102
is formed in the substrate
100
to define the active region. A gate oxide layer
104
and a polysilicon layer
106
are then sequentially formed on the substrate
100
.
Referring to
FIG. 1B
, the polysilicon layer
106
and the gate oxide layer
104
are defined to form a gate structure
108
, in which the gate structure
108
is formed with the polysilicon layer
106
a
and the gate oxide layer
104
a
. Using the gate structure
108
as a mask, an ion implantation is conducted to form a lightly doped source/drain region
110
in the substrate
100
at both sides of the gate structure
108
. A spacer
112
is then formed on the sidewall of the gate structure
108
. Further using the gate structure
108
and the spacer
112
as masks, an ion implantation is conducted to form a heavily doped region
114
. Thereafter, a dielectric layer
116
is formed to cover the substrate
100
.
Continuing to
FIG. 1C
, a portion of the dielectric layer
116
is removed to form a contact window
118
, exposing a portion of the source/drain region
114
. Subsequently, a bit-line and a bottom electrode structure of a dynamic memory cell device are formed.
In the above approach, misalignment often occurs during the formation of the contact window in the dielectric layer. As a result, the formation of the contact window requires a smaller design rule to avoid the unexpected electrical connection resulting from the misalignment.
Furthermore, during the formation of the contact window, it is necessary to etch a substantial thickness of the dielectric layer to expose the source/drain region, which further increases the technical difficulty of the manufacturing process. The aspect ratio of the node contact window formed according to the conventional approach is also very high; the formation of the storage node contact electrode in the node contact window therefore becomes very difficult. The storage node contact electrode formed may have voids or the problem of an increased resistance between the storage node contact electrode and the drain region may arise.
SUMMARY OF THE INVENTION
Based on the foregoing, the present embodiment of the invention provides a fabrication method for an ultra short channel of a device which comprises a self-aligned landing pad. The method is applicable to the manufacturing of a dynamic random access memory device in which an oxide layer is formed on a substrate comprising device isolation structures. A first opening is then formed in the oxide layer to define the gate structure region. Thereafter, a pad oxide layer is formed in the opening covering the substrate followed by forming a spacer on the sidewall of the first opening. Using the spacer as an etching mask, a portion of the pad oxide layer is removed to form a second opening exposing the substrate. A gate oxide layer is then deposited in the second opening. A conductive layer serving as a gate is then formed, filling the second opening. After this, the oxide layer is defined to form a third opening exposing the substrate and defining the territory for the source/drain region. An ion implantation is then conducted on the substrate of the third opening to form a heavily doped region of the source/drain region. A landing pad is subsequently formed to fill the third opening, wherein the landing pad is served as an elevated source/drain region and is electrically connected to the heavily doped region. The spacer is then removed to form a fourth opening, exposing the pad oxide layer. After this, an ion implantation is conducted on the substrate of the fourth opening to form a lightly doped source/drain region in the substrate. A nitridation process is further conducted to form a protective layer on the conductive layer. A defined dielectric layer is further deposited on the substrate with contact windows, which dielectric layer exposes a portion of the landing pad, wherein the contact windows include a bit line contact window and a node contact window. Subsequently, a bit line and a bottom electrode structure, which are electrically connected to the landing pad, are formed in the contact window.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6022776 (2000-02-01), Lien et al.
Bowers Charles
Charles C. H. Wu & Associates
Huynh Yennhu B.
United Microelectronics Corp.
Wu Charles C. H.
LandOfFree
Fabrication method for ultra short channel device comprising... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication method for ultra short channel device comprising..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method for ultra short channel device comprising... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473075