Fabrication method for single and dual gate spacers on a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S595000, C257SE21626

Reexamination Certificate

active

11217369

ABSTRACT:
A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.

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Chung, “Dual GC Spacer Process Flow”, ProMOS DIT 1-T3, Nov. 12, 2004, pp. 1-6.

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