Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-04-08
2008-04-08
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C257SE21626
Reexamination Certificate
active
07354837
ABSTRACT:
A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.
REFERENCES:
patent: 6197632 (2001-03-01), Bronner et al.
patent: 6500765 (2002-12-01), Kao et al.
patent: 6727543 (2004-04-01), Lin
patent: 6737308 (2004-05-01), Kim
Williams, K.R., Gupta, K.; “Etch Rates for Micromachining Processing—Part II”, Journal of Microelectromechanical Systems, vol. 12, No. 6, Dec. 2003.
Williams, K.R., Gupta, K.; “Etch Rates for Micromachining Processing”, Journal of Microelectromechanical Systems, vol. 5, No. 4, Dec. 1996.
Wolf. S., Tauber, R.N.; Silicon Processing for the VLSI Era vol. 1—Process Technology; Lattice Press; 2000.
Chung, “Dual GC Spacer Process Flow”, ProMOS DIT 1-T3, Nov. 12, 2004, pp. 1-6.
Chung Chao-Hsi
Hu Chu-Chun
Wang Chih-Cheng
Baumeister B. William
Birch & Stewart Kolasch & Birch, LLP
ProMOS Technologies Inc.
Wilson Bryan E
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