Fabrication method for semiconductor memory device

Details Fabrication method for semiconductor memory device Fabrication method for semiconductor memory device

1997-11-26

2000-10-24

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438256, 438397, H01L 218242

Patent

active

061366455

ABSTRACT:
A fabrication method for a semiconductor memory device, which forms a capacitor over a bit line, includes the steps of forming an active region pattern on a semiconductor substrate, forming a field oxide region for electrically isolating single devices in the semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a first conductive film to serve as a gate electrode on the gate insulating film, forming a first insulating film having a first etching characteristic on the first conductive film, and patterning the first insulating film and the first conductive film to form a plurality of word line patterns. Next a second insulating film, having the first etching characteristic, is formed over the semiconductor substrate, and is etched to form sidewall spacers at lateral walls of each word line pattern. A third insulating film is then formed over the semiconductor substrate, and removed from regions where a bit line is to be formed. This exposes the active region and forms a bit line trench pattern. A bit line is then formed with portions thereof disposed in the bit line trench pattern, and a capacitor is formed over the bit line. The different etching characteristics of the insulating films allows for a larger contact hole to be formed thereby improving the contact hole aspect ratio.

REFERENCES:
patent: 5014103 (1991-05-01), Ema
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5512163 (1996-04-01), Warfield
patent: 5733809 (1998-03-01), Dennison et al.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, pp. 201-203, 1990.
Shibahara, et al., "1GDRAM Cell with Diagonal Bit-Line (DBL) Configuration and Edge Operation MOS (EOS) FET" IEEE (1994) p.p. 26.5.1-26.5.4.

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