Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-01-31
1999-06-01
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438486, 438487, 438483, 438508, 438530, 438542, 438557, 438575, 148DIG61, H01L 218238
Patent
active
059083077
ABSTRACT:
Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.
REFERENCES:
patent: 4617066 (1986-10-01), Vasudev
patent: 4904611 (1990-02-01), Chiang et al.
patent: 5147826 (1992-09-01), Liu et al.
patent: 5342793 (1994-08-01), Santangelo et al.
patent: 5407838 (1995-04-01), Ohmishi et al.
patent: 5470619 (1995-11-01), Ahn et al.
S. Prussin, et al., Role of Ion Mass, Implant Dose, and Wafer Temperature on End-of-Range Defects, J. Electrochem. Soc., vol. 137, No. 6, 1912-1914, The Electrochemical Society, Inc., (Jun. 1990).
E. D'Anna, et al., Multilayer Titaninum Nitride and Silicide Structures Synthesized by Multipulse Excimer Laser Irradiation, Elsevier Science Publishers B.V., 353-357, Applied Surface Science 54, (1992).
V. Bohac, et al., Tungsten Silicide Formation by XeC1 Excimer-Laser Irradiation of W/Wi Samples, Applied Physics A. Solids and Surfaces, 391-396, Applied Physics A 56, (1993).
E. D'Anna, et al., Laser Synthesis of Metal Silicides, Applied Physics A. Solids and Surfaces, 325-335, Applied Physics A 45, (1988).
Richard B. Fair, Damage Removal/Dupant Diffusion Tradeoffs in Ultra-Shallow Implanted p.sup.+ -n Junctions, IEEE Transactions on Electron Devices, vol. 37, No. 10, 2237-2242, (Oct. 1990).
Toshimitsu Akane, et al., Two-Step Doping Using Excimer Laser in Boron Doping of Silicon, Jpn. J. Appl. Phys., vol. 31, Part 1, No. 12B, 4437-4440 (Dec. 1992).
P.G. Carey, et al., A Shallow Junction Submicrometer PMOS Process Without High-Temperature Anneals, IEEE Electron Device Letters, vol. 9, No. 10, 542-544, (Oct. 1988).
S. Acco, et al., Avoiding End-of-range Dislocations in Ion-implanted Silicon, Elsevier Science S.A., Materials Science and Engineering B34, 168-174, (1995).
Kramer Karl-Josef
Talwar Somit
Verma Guarav
Weiner Kurt
Brown Peter Toby
Jones Allston L.
Pham Long
Ultratech Stepper, Inc.
LandOfFree
Fabrication method for reduced-dimension FET devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication method for reduced-dimension FET devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method for reduced-dimension FET devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-951257