Fabrication method for non-volatile memory

Details Fabrication method for non-volatile memory Fabrication method for non-volatile memory

2003-06-18

2004-11-02

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S266000

Reexamination Certificate

active

06812083

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a fabrication method of a single poly one time programmable non-volatile memory (NVM) cell or a single poly multiple time programmable non-volatile memory cell, and more particularly, to a method allowing an increase in speed of data writing by adjusting coupling capacitors of a metal oxide semiconductor transistor in the NVM cell.
2. Description of the Prior Art
In recent years, because NVM devices can maintain data after power-off and are rewritable, they are used to record long-term data. The read/write speed of a NVM is a reference to judge the quality of the NVM.
Referring to
FIG. 1
,
FIG. 1
is a sectional drawing of a non-volatile memory cell
10
according to the prior art. The NVM cell
10
includes a first PMOS transistor
12
and a second PMOS transistor
14
. The first PMOS transistor
12
and the second PMOS transistor
14
are formed on an n-well
16
. The second PMOS transistor
14
and the first PMOS transistor
12
are electrically connected serially to the first PMOS transistor
12
sharing a second P
+
doped region
20
. The first PMOS transistor
12
includes a first P
+
doped region
18
used to as a drain, and a control gate
24
made between the first P
+
doped region
18
and the second P
+
doped region
20
(a source). The second PMOS transistor
14
is a floating gate transistor, and includes the drain
20
(the second P
+
doped region
20
), a third P
+
doped region
22
used as a source, a floating gate
26
made by single layer poly crystal, and a floating gate oxide film
32
between the floating gate
26
and the n-well
16
.
Each electrode of the first PMOS transistor
12
and the second PMOS transistor
14
in the NVM cell
10
according to the prior art can be given different voltages to perform different programmable actions (writing data or reading data). For example, referring to
FIG. 1
, when writing data to the NVM cell
10
, a bit line voltage V
1
=0V is applied to the P
+
doped region
22
of the second PMOS transistor
14
, and a word line voltage V
2
=0V is applied to the control gate
24
. A well voltage V
3
=5V is applied to n-well
16
so the floating gate
26
of the second PMOS transistor
14
remains in a floating status, and a source line voltage V
1
=5V is applied to the third P
+
doped region
18
so the source
18
of the first PMOS transistor
14
and n-well
16
have the same electric potential. At this time, a first P-type channel under the control gate
24
is formed, so that the second P
+
doped region
20
and the first P
+
doped region
18
have the same electric potential. Because the floating gate
26
of the second PMOS transistor
14
is under a low voltage (for example, 3~4V) according to capacitive coupling effect, a second P-type channel is opened under the floating gate
26
. Collision of holes in the second P-type channel generates hot electrons. The hot electrons quickly cross the floating gate oxide film
32
and are trapped in the floating gate
26
.
Referring to
FIG. 2
,
FIG. 2
is a graph relating dropout voltage between the floating gate
26
and the source
22
of the NVM cell
10
, and the gate current I flowing in the second P-type channel. Solid lines and dotted lines represent different biasing voltages. As in
FIG. 2
, when dropout voltage V
fs
is near a threshold voltage V
th
, the gate current I is near the maximum gate current I
max
. The value of the gate current I directly affects speed of writing data (and reading data) to the NVM cell
10
. When the dropout voltage V
fs
between the floating gate
26
and the source
22
of the second PMOS transistor
14
is larger or smaller than the threshold voltage V
th
of the PMOS transistor
14
, which causes the gate current I to flow in the second P-type channel at a rate less than the largest gate current I
max
, the speed in the floating gate
26
of the second PMOS transistor
14
affects data writing to the NVM cell
10
. In addition, the value of the threshold voltage V
th
of the maximum gate current I
max
is ranging from 0.5V to 1.5V.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a fabrication method of a single poly one time programmable non-volatile memory cell or a single poly multiple time programmable non-volatile memory cell to solve the above-mentioned problem.
According to the claimed invention, a fabrication method for a metal oxide semiconductor transistor of a NVM includes forming a first doped region, a second doped region, and a third doped region on a well; forming a control gate between the first doped region and the second doped region; forming a floating gate between the second doped region and the third doped region; providing a first biasing voltage between the first doped region and the control gate such that the first doped region and the second doped region are conductive; providing a second biasing voltage between the second doped region and the well, so as to generate a channel current between the second doped region and the third doped region, and generate a gate current; wherein if a voltage difference between the third doped region and the floating gate is smaller than the threshold voltage of the floating gate device, increasing a capacitance between the floating gate and the third doped region to larger than a total capacitance synthesized between the floating gate and the well, the floating gate and the second doped region, and the floating gate and the control gate; or increasing a capacitance between the floating gate and the control gate to larger than a total capacitance synthesized between the floating gate and the third doped region, the floating gate and the well, and the floating gate and the second doped region; wherein if a voltage difference between the third doped region and the floating gate is larger than the threshold voltage of the floating gate device, decreasing the capacitance between the floating gate and the third doped region to smaller than the total capacitance synthesized between the floating gate and the well, the floating gate and the second doped region, and the floating gate and the control gate; and decreasing the capacitance between the floating gate and the control gate to smaller than the total capacitance synthesized between the floating gate and the third doped region, the floating gate and the well, and the floating gate and the second doped region.
It is an advantage of the claimed invention that a single poly one time programmable non-volatile memory cell or a single poly multiple time programmable non-volatile memory cell fabricated according to the claimed invention method can write data faster than the NVM cell made according to the prior art.
These and other objectives of the claimed invention will not doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5089866 (1992-02-01), Iwasa
patent: 5416735 (1995-05-01), Onishi et al.
patent: 5596523 (1997-01-01), Endoh et al.
patent: 6115285 (2000-09-01), Montanari et al.
patent: 6285592 (2001-09-01), Kubota
patent: 6444554 (2002-09-01), Adachi et al.
patent: 6504755 (2003-01-01), Katayama et al.
patent: 6630381 (2003-10-01), Hazani
patent: 6657245 (2003-12-01), Tanaka et al.
patent: 6678190 (2004-01-01), Yang et al.
patent: 06268180 (1994-09-01), None
patent: 08264522 (1996-10-01), None
patent: 2001-110916 (2001-04-01), None

Affiliated with

Also associated with

Rating

Fabrication method for non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication method for non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method for non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3333689