Fabrication method for mask read only memory device

Details Fabrication method for mask read only memory device Fabrication method for mask read only memory device

2002-05-24

2004-09-14

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S142000, C438S257000, C438S594000

Reexamination Certificate

active

06790730

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 91110594, filed May 21, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a read only memory device. More particularly, the present invention relates to a fabrication method for a mask read only memory (ROM) device.
2. Description of Related Art
The read only memory device provides the non-volatile property, wherein the stored information is retained even power is interrupted. As a result, the read only memory device is incorporated into many electronic products to maintain a normal operation for the products. The mask read only memory device is the most fundamental type of read only memory device. A typical mask ROM device uses a channel transistor as the memory device. The programming of a mask ROM device is accomplished by selectively implanting ions to an identified channel region. By altering the threshold voltage, the control of the “on” and the “off” of the memory device is thus achieved.
A typical mask read only memory device comprises a polysilicon word line, that crosses over the bit line. The region under the word line and between the bit lines is the channel region of the memory device. Whether ions are implanted to the channel region determines the storage of the binary digit of either “0” or “1”, wherein the implanting of ions to the identified channel region is known as coding implantation.
Under the current development of increasing the device integration, devices are being scaled down according to the design rule. In order to prevent the short channel effect resulted from the reduction of the device dimension, a shallow junction or an ultra shallow junction is used for the buried bit line, which is formed by pocket ion implantation. A shallow junction or an ultra shallow junction can improve the short channel effect resulted from the reduction of the device dimension. However, the depth of the junction of the buried bit line becomes shallower, the resistance of the buried bit line thereby increases.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a fabrication method for a mask ROM device, wherein the short channel effect resulted from the reduction of the device dimension is prevented.
The present invention provides a fabrication method for a mask ROM device, wherein an increase of the resistance due to a shallow source/drain junction is also prevented.
The fabrication method for a mask ROM device according to the present invention includes providing a substrate, wherein a doped conductive layer is formed on the substrate. The doped conductive layer is then patterned to form a plurality of bar shaped doped conductive layers. Thermal oxidation is further performed to form a dielectric layer on the substrate and on the bar shaped doped conductive layers. A plurality of diffusion regions are concurrently formed in the substrate under the bar-shaped conductive layers. Thereafter, a patterned conductive layer is formed on the dielectric layer.
As disclosed in the above, the source/drain regions of the present invention are the diffusion regions formed by the diffusion of dopants from the bar-shaped doped conductive layers. The junction of the source/drain region is thereby shallower to prevent the short channel effect generated from the reduction of the device dimension.
Further, the bit line of the present invention includes the raised bit line formed by the doped conductive layer on the substrate. The thickness of the bit lines is thus sufficient to prevent an increase of the resistance resulted from a shallower junction.
Additionally, the gate dielectric layer (which is the part of the dielectric layer that forms on the substrate surface) and the insulation layer on the bar-shaped doped conductive layers are formed in a same processing step. An extra processing step for forming the insulation layer on the bar shaped conductive layers is thus obviated.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5780339 (1998-07-01), Liu et al.
patent: 6242307 (2001-06-01), Sheu
patent: 6607957 (2003-08-01), Fan et al.

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