Fabrication method for integrated circuits

Details Fabrication method for integrated circuits Fabrication method for integrated circuits

1996-11-14

1998-06-16

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438666, 438669, H01L 2128

Patent

active

057670110

ABSTRACT:
A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

REFERENCES:
patent: 4499484 (1985-02-01), Tanizawa et al.
patent: 4928164 (1990-05-01), Tanizawa
patent: 5422317 (1995-06-01), Hua et al.

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