Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-28
2001-02-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S304000
Reexamination Certificate
active
06194279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a semiconductor substrate. More particularly, the present invention relates to a fabrication method for a gate spacer.
2. Description of Related Art
Concurrent with an increase in semiconductor device integration, it is common to decrease the size of the circuit structure device according to design rules, which gradually minimizes an integrated circuit (IC) device. However, the circuit resistance increases as the size of the semiconductor circuit design decreases without any material change.
Conventionally, several methods have been developed to solve the problem of increased sheet resistance from the interface between a polysilicon gate and a source/drain (S/D) region. One of these methods is a self-aligned silicide (salicide) process, which forms a silicide on the surface of the polysilicon gate and the S/D region to reduce the sheet resistance of the polysilicon gate and the S/D region.
However, since the surface area of the polysilicon gate and the S/D region for forming the silicide has become very small in the deep sub-micron process, a narrow linewidth effect readily occurs in the salicide process. One conventional method of increasing the area for forming the silicide is to over-etch the gate spacer, so that the height of the spacer is reduced. As a result, the top edge of the polysilicon gate is exposed to increase the surface area for forming the silicide.
Although this solves the problem related to the sheet resistance of the polysilicon gate, other problems develop. As the over-etching time lengthens, the height of the spacer decreases and the width of the spacer also reduces. Despite the increased surface area of the gate for forming the silicide, the width reduction of the spacer causes other related problems; for example, the width reduction of the lightly doped drain (LDD) leads to an enhanced short channel effect. Thus, it is not easy to control the duration of the over-etching process, which reduces the height of the spacer. In addition, the substrate surface of the S/D region is exposed during the over-etching process, so that the surface is damaged as a result of an increased etching time, leading to the problem of leakage current.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for a gate spacer in which the height and width of a spacer can be independently controlled. The invention not only provides a surface area of the gate, which increases the silicide formation to reduce a resistance of the gate polysilicon layer, but also controls the width of the spacer. Therefore, the width of the spacer decreases with its height, while no damage is done to the substrate.
As embodied and broadly described herein, the invention provides a fabrication method for a gate spacer. The method includes providing a substrate and forming a gate on the substrate, wherein the gate is covered by a spacer, such as a SiN
x
layer. A liner oxide layer is selectively formed between the gate and the spacer to improve the adhesion. A S/D region is formed by doping at either sides of the gate on the substrate. The substrate is then covered with a sacrificial layer, such as a SiO
x
layer. A part of the sacrificial layer is removed until the surface of the remaining sacrificial layer is lower than the top surface of the gate. A part of the spacer is removed until a remaining spacer has a top portion between a top surface of the gate and a top surface of the sacrificial layer. As a result, the top edge of the gate spacer is exposed to increase the exposed area of the gate. The sacrificial layer is then removed, while a silicide layer, such as a SiTi
x
layer, is formed on the exposed surface of the gate and the S/D region to further reduce the sheet resistance.
According to the present invention, the height and width of the gate spacer can be independently controlled. Therefore, the sheet resistance of the polysilicon gate is reduced by increasing the reactive surface area for forming the silicide, while the damage to the substrate, which would otherwise induce the leakage current, is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5851890 (1998-12-01), Tsai et al.
patent: 5923986 (1999-07-01), Shen
patent: 5953615 (1999-09-01), Yu
patent: 6015747 (2000-01-01), Lopatin et al.
Chen Chun-Lung
Cheng Wen-Hua
Hsiao Hsi-Mao
Lin Hsi-Chin
Le Dung A
Nelms David
Thomas Kayden Horstemeyer & Risley
United Silicon Incorporated
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