Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-28
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S761000
Reexamination Certificate
active
06319820
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89105154, filed Mar. 21, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a dual damascene structure in a dielectric material.
2. Description of the Related Art
As the levels of an integrated circuit continue to increase, the demands on the metallization process for the wiring technique of a semiconductor wafer increase correspondingly. In the conventional metallization process, a patterned photoresist layer is formed for each metal layer in the etching of the individual metal layer in order to form the metal conductive line. The metal layer is also required to connect to the device region of a semiconductor substrate for the wafer fabrication. A vertical interconnect is formed by forming a hole in the insulation layer used to separate the metal layers. Forming holes in different insulation layers would require performing a photolithography process on each insulation layer. As the number of layers that requires metallization increases, the number of photolithography processes increases correspondingly. The manufacturing of a semiconductor wafer thereby becomes more complicated. Currently in the ultra large scale integration (ULSI), to concurrently form a horizontal trench and a vertical hole using a single photoresist process in metallization and to employ the similar technique to form a multi-level interconnect on a highly integrated wafer have thereby posed a great challenge in the semiconductor industry.
When the technology has evolved from the very large scale integration (VLSI) to the ultra large scale integration (ULSI), it is necessary to improve electron migration for the increase of the speed of a device and the computer operation. It is therefore essential for the semiconductor industry to develop new methods and technologies for the manufacturing of a highly integrated semiconductor wafer. In a highly integrated wafer, the actual distance between devices is reduced to provide not only a faster transmission of an electrical signal, the resistance generated in signal transmission is also reduced. On the other hand, the ultra large scale integration is formed with very small devices and the multi-level interconnects. The operation of the multi-level interconnects hence must have a minimum increase of resistance in signal transmission, and most importantly, impedance matching must be avoided.
A semiconductor wafer usually comprises one or multiple conductive lines formed thereon. These conductive lines are isolated from each other with an insulation layer. An insulation layer is also used to isolate the devices near the semiconductor surface. These conductive lines are interconnected to each other and are connected to the devices at the appropriate regions. The metal conductive lines are connected to each other by filling a hole formed in the insulation layer with a metal layer. Conventionally, there are many approaches to form the metal line and the multi-level interconnects. The hole that passes through the insulation layer to allow the interconnection between the metal conductive lines is known as the via hole. The hole that passes through the insulation layer to allow the connection with the underlying devices is known as the contact hole. These holes are normally formed by depositing an insulation layer on the semiconductor substrate, followed by etching the insulation layer. Thereafter, a metal layer is deposited to cover the insulation layer and to fill the holes. The metal layer is then etched to form the metal conductive lines. The first metal layer is electrically connected with the underlying device through a contact hole. Similarly, the second metal layer is electrically connected with the underlying metal layers through the via hole. Furthermore, these holes are filled with metal to form the metal plugs, followed by planarizing the metal layer to the surface of the insulation layer. Another metal layer is further deposited as contacts of the metal plugs, followed by etching the deposited metal layer to complete the formation of the individual conductive layer.
In order for the metal interconnect or the metal plugs to have a solid contact region, the spaces reserved for the metal interconnects and the holes must increase to cover the overlay error generated in printed circuit board manufacturing or to cover the processing variations. This type of design rule, however, would increase the dimension of the circuit and significantly reduces the density of the device. The self-aligned process is thereby developed as the wafer becomes miniaturized.
Furthermore, forming contacts between the metal layers in the substrate also encompasses other problems. While the insulation layer is etched to form the contact hole, the sidewall of the contact hole needs to recline a certain degree to ensure an excellent continuity of the metal layer. It is, however, highly probable that the deposited metal layer is discontinuous if the sidewall of the contact hole is reclined too steep. Although a gradually reclining sidewall would ensure the continuity of the metal conductive line, the density of the contacts would be reduced. In addition, such an approach to form the contacts would lead to an irregular and unplanarized surface. As a result, difficulties in manufacturing the subsequent interconnect layer increase.
FIG. 1
is a schematic, cross-sectional view showing the manufacturing of a semiconductor device according to the prior art. As shown in
FIG. 1
, a substrate
10
comprising a device region
11
is provided. A first insulation layer
12
is formed, wherein a contact window
14
is defined in the insulation layer
12
. A first metal layer
13
is deposited on the first insulation layer
12
, wherein the first metal layer
13
is connected to the device region
11
through the contact window
14
. Similarly, a second metal layer
16
is connected to the first metal layer
13
through via hole
17
defined in the second insulation layer
15
. A third insulation layer
18
is further formed to serve as a passivation layer. The structure having the irregular surface as illustrated in
FIG. 1
would lead to the problem of an unreliable device. For example, when the insulation layer between the different metal layers becomes thinner, a short circuit may occur in the S region between the first metal layer and the second metal layer, whereas when the metal layers become thinner, an open circuit may occur in the O region.
A conventional approach to solve the aforementioned problem is by dual damascene processing. The dual damascene process is performed on an insulation layer, wherein the insulation layer is formed on a substrate. After the insulation layer is planarized, the insulation layer is defined to form a horizontally oriented trench and a vertically oriented hole concurrently. Through the hole in the first insulation layer, the metal conductive line is connected with the underlying device region. Through hole in an upper insulation layer, the metal conductive line is connected with another metal layer. A metal layer is further deposited on the substrate where the above structure is already formed to fill the trench and the hole, forming the metal conductive line and the metal plug. Chemical mechanical polishing (CMP) is further conducted to planarize the surface and to complete the dual damascening of the horizontal trench and the vertical hole.
FIGS. 2A
to
2
B are cross-sectional views showing the manufacturing of a dual damascene structure according to the prior art. As shown in
FIG. 2A
, a silicon dioxide layer
22
is deposited on a substrate
21
, comprising a conductive region
20
(the conductive region can be a metal or a metal silicide material). Photolithography and etching are conducted to form a via hole
23
, which is connected to the conductive region
20
. As shown in
FIG.
Huang Jiawei
J. C. Patents
Luk Olivia
Niebling John F.
Winbond Electronics Corp.
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