Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-05-19
2001-10-02
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S668000, C257S686000, C257S723000, C257S784000, C257S787000, C361S723000, C361S773000
Reexamination Certificate
active
06297547
ABSTRACT:
BACKGROUND
The invention relates to mounting multiple semiconductor dies in a package.
A typical semiconductor device starts with a single die that is sawed from a silicon wafer. Circuitry is formed on the die by a series of deposition, masking, diffusion, etching, and implanting steps. The back of the die is bare. The die is attached to the leadframe by an adhesive layer that can also serve to electrically insulate the die from the leadframe. The die is then electrically connected to the leadframe by wirebonding the lead fingers of the leadframe to a bonding pads disposed around the periphery of the die (conventional configuration), or down the center of the die in a lead-on-chip (LOC configuration). After wirebonding, the die and the leadframe are encapsulated in a molded plastic package that is hermetically sealed to protect the die from moisture and physical stress. The lead fingers extend outside the plastic package to form leads that are folded down the side of the plastic package.
Various methods have been developed to increase package density. For example, U.S. Pat. No. 5,012,323, having the same assignee as the present application discloses a semiconductor package incorporating a pair of conventional semiconductor dies (a first die mounted over a second die) on a single lead frame. The bonding pads on a conventional die are located on its periphery. To enable the bonding pads of the second die to be wirebonded to the leadframe, the rectangular surface area of the first die (mounted over the second die) is shown as being smaller than that of the second die.
SUMMARY
In accordance with one aspect of the present invention, a multiple die package includes a pair of dies having bonding pads and front surfaces on which the bonding pads are located, the front surfaces facing oppositely from one another. The package also includes a lead frame. One of the dies is secured on the leadframe. A bond pad of that die is electrically connected to the leadframe.
In accordance with another aspect of the present invention, a multiple die package includes a pair of dies having bonding pads and front surfaces on which the bonding pads are located, the front surfaces facing in the same direction. The package also includes a leadframe. At least one of the dies is secured to the leadframe. A spacer is used for spacing the dies from one another.
In accordance with yet aspect of the present invention, a method involves mounting multiple semiconductor dies on a single leadframe by stacking at least two semiconductor dies having the same rectangular dimensions on top of one another. The stacked dies are electrically connected to the leadframe.
In accordance with but another aspect of the present invention, a method of connecting multiple semiconductor dies having bonding pads and a single leadframe having lead fingers includes mounting a first semiconductor die on the lead fingers of the leadframe. A second semiconductor die is stacked on the first semiconductor die. The bonding pads of the semiconductor dies are electrically connected to the lead fingers of the leadframe.
In accordance with another aspect of the present invention, a semiconductor device includes a plurality of semiconductor dies having the same rectangular dimensions. A leadframe has lead fingers to which the semiconductor dies are mounted. Conductors electrically connect the dies to the leadframe.
In accordance with yet another aspect of the present invention, a semiconductor device has a leadframe with a first surface, a second surface opposite the first surface, and lead fingers. A first die is located on the first surface, the first die having bond pads which are electrically contacted to the lead fingers on the first surface of the leadframe. A second die is located on the second surface, the second die having bond pads which are electrically contacted to the lead fingers on the second surface of the leadframe.
In accordance with but another aspect of the present invention, an integrated circuit package has a leadframe with first and second surface. A support member is mounted to a first surface of the leadframe. A first die is mounted to the support member, and a second die is mounted to a second surface of the leadframe.
Advantages of the invention include one or more of the following: a higher density integrated circuit device multiple dies having the same size may be mounted on a single leadframe, and a semiconductor package having both LOC and conventional dies. Other advantages will become apparent from the following description.
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Chambliss Alonzo
Chaudhuri Olik
Micro)n Technology, Inc.
Trop Pruner & Hu P.C.
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