Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-06-12
2004-05-25
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S118000, C438S612000, C174S255000
Reexamination Certificate
active
06740540
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to fabrication methods for circuit boards, and more particularly, to a method for fabricating a substrate or a printed circuit board (PCB).
BACKGROUND OF THE INVENTION
In conventional processes for fabricating a circuit board such as substrate or printed circuit board (PCB), first, a core layer is prepared by fiber glass, epoxy resin, polyimide, FR4 resin or BT resin, etc. Then, at least a copper film is attached to the core layer, and patterned to form a plurality of conductive traces on the core layer. Since the trace-forming process is well known in the art, it is not to be further described herein.
After that, solder mask is applied over the conductive traces to form protective coating on the core layer, so as to protect the conductive traces against oxidation or short circuit without affecting electricity thereof. In more detail, solder mask is first applied over the core layer by halftone-printing, roller-coating, screen-coating or electrostatic-spraying processes. Then, undesired part of solder mask is removed through the use of exposure and development techniques; remaining solder mask is baked under high temperature and become cured to form the protective coating.
However, the above conventional circuit board is inherent with significant drawbacks. For example, during the process for applying solder mask over the core layer, halftone-printing or roller-coating processes are performed in multiple times for accumulating solder mask with desired thickness; this considerably increases process complexity in fabrication. And, accumulated thickness of solder mask is hardly controlled, which may adversely affect planarity and electrical stability of the circuit board. Moreover, in the baking process under high temperature, due to mismatch in coefficient of thermal expansion (CTE) between solder mask and the core layer of the circuit board, thermal stress would be generated and causes warpage of the circuit board. Furthermore, during coating solder mask over the core layer, air would be possibly trapped in solder mask to form voids, which facilitates the occurrence of popcorn effect in subsequent fabrication processes. In addition, solder mask is poorly adhered with copper traces formed on the core layer; this would easily cause delamination at interface between solder mask and conductive traces, and undesirably affect quality and reliability of the circuit board.
Therefore, there is disclosed another method for fabricating a circuit board. This fabrication method for a circuit board
1
can be carried out by process steps illustrated in
FIGS. 5A
to
5
E. Referring to
FIG. 5A
, the first step is to prepare a core layer
10
, with predetermined patterning of copper conductive traces
11
being formed on two opposing surfaces of the core layer
10
. A plurality of vias
12
are formed to penetrate through the core layer
10
, and plated with copper on inner walls thereof The core layer
10
can be made of a material same as that used for a conventional circuit board, such as epoxy resin, polyimide resin, FR4 resin, etc.
Referring to
FIG. 5B
, the next step is to apply a non-solderable material
14
in predetermined thickness over an aluminum film
13
. The non-solderable material
14
is preferably made of a material having coefficient of thermal expansion (CTE) similar to or same as that of the core layer
10
.
Then, the non-solderable material
14
together with the aluminum film
13
are attached to the core layer
10
for covering the conductive traces
11
, in a manner that the non-solderable material
14
is interposed between the aluminum film
13
and the core layer
10
. Under predetermined pressure (10-40 kgw/cm
2
) and temperature (185° C.), the non-solderable material
14
becomes cured and fully fills the vias
12
and other fine holes of the core layer
10
, and thus the non-solderable material
14
forms a desired protective layer for protecting the conductive traces
11
against oxidation and external impact.
Referring to
FIG. 5C
, a layer of photo resist
15
is applied over an exposed surface of the aluminum film
12
. The photo resist
15
is selectively removed by using exposure and development processes, so as to expose predetermined part of the aluminum film
13
, wherein the exposed part of the aluminum film
13
corresponds to predetermined positions of the underneath conductive traces
11
to be later exposed for use as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.
Referring to
FIG. 5D
, remaining photo resist
15
and exposed part of the aluminum film
13
are etched away by using chemical solvents, so as to expose predetermined part of the non-solderable material
14
covering bond pad or finger positions of the underneath conductive traces
11
. Then, the exposed part of the non-solderable material
14
is removed by plasma etching technique, such that bond pads or fingers of the conductive traces
11
can be desirably exposed.
Finally referring to
FIG. 5E
, remaining aluminum film
13
is chemically etched to completely expose the non-solderable material
14
.
The above-fabricated circuit board
1
can desirably eliminate those outlined drawbacks for the foregoing conventional circuit board. For example, one single step of applying non-solderable material
14
allows to desirably achieve predetermined thickness for the non-solderable material
14
, thereby effectively reducing complexity and costs in fabrication. Moreover, since the non-solderable material
14
has coefficient of thermal expansion similar to or same as that of the core layer
10
, the circuit board II can be assured with structural intactness without being warped by thermal stress, thus making production yield greatly improved. In addition, the non-solderable material
14
is firmly attached to the core layer
10
and conductive traces
11
under condition of certain temperature and pressure, and thus air is hardly trapped in the non-solderable material
14
, so that popcorn effect or delamination would significantly reduce in occurrence, making quality and reliability of the circuit board
1
firmly assured.
However, the above fabrication method for the circuit board
1
still has considerable drawbacks. First, conductive traces
11
formed on the core layer
10
are covered by multi-layered structure including the non-solderable material
14
, aluminum film
13
and photo resist
15
; as such, it is difficult to visually recognized predetermined part of the conductive traces
11
to be exposed through such multi-layer structure. In order to precisely position corresponding part of the photo resist
15
aligned with the part of the conductive traces
11
to be exposed, X-ray fluoroscopy is usually adopted to determine fiducial marks on the photo resist
15
. However, X-ray fluoroscopy still possibly causes positioning inaccuracy up to ±75 &mgr;m, making etched part of the aluminum film
13
and non-solderable material
14
not precisely positioned in correspondence with the predetermined exposed part of the conductive traces
11
, which deteriorates production yield of fabrication circuit boards
1
.
Moreover, during fabrication processes, with the photo resist
15
, aluminum film
13
and non-solderable material
14
being stacked on the core layer
10
, for exposing predetermined part of the conductive traces
1
, it needs to in turn remove the photo resist
15
, aluminum film
13
and non-solderable material
14
, thereby making process complexity and costs in fabrication undesirably increased.
Furthermore, the non-solderable material
14
is partly removed by plasma-etching technique; for suitably applying the plasma-etching process, the non-solderable material e.g. epoxy resin
14
cannot be added with fillers, which makes the non-solderable material
14
relatively low in structural strength, thereby not able to provide the circuit board
1
with high rigidity or mechanical strength.
In addition, the plasma-etching technique is used to selectively remove
Bai Jin-Chuan
Tsai Chung-Che
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Nguyen Tuan H.
Ultra Tera Corporation
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