Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-05-17
2004-11-23
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S248000
Reexamination Certificate
active
06821843
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a fabrication method for a dynamic random access memory (DRAM), and more particularly to a fabrication method for an array area and a support area of a DRAM cell.
2. Description of the Related Art
A DRAM cell comprises memory elements in an array area and support circuit devices in a support area, in which the support circuit devices are used to control address and data transport of the memory elements. In order to reduce the size of individual DRAM cells and increase their density, three dimensional structures have been developed in the DRAM cell, such as a vertical transistor and a deep trench capacitor, which result in smaller memory area and higher operating speed. However, conventional processes for a gate dielectric layer and a gate conductive layer in the support area are combined with processes for word lines in the array area, thus the procedure is complicated and requires numbers of photolithography steps, resulting in reduced accuracy in transferring patterns.
FIGS. 1A
to
1
I are cross-sections of a conventional fabrication method for an array area and a support area of a DRAM cell.
In
FIG. 1A
, a semiconductor silicon substrate
10
comprises an array area I and a support area II. A first shallow trench isolation (STI) structure
12
is formed within the array area I for separating memory elements from each other, and a second STI structure
14
is formed in a transition region between the array area I and the support area II for separating elements of the array area I from elements of the support area II. A pad oxide layer
16
and a pad nitride layer
18
are patterned on the substrate
10
to define a deep trench DT within the array area I. A deep trench capacitor
20
is formed at the lower portion of the deep trench DT, a vertical transistor
24
is formed at the upper portion of the deep trench DT, and an oxide isolating layer
22
is sandwiched between the deep trench capacitor
20
and the vertical transistor
24
. The vertical transistor
24
comprises a gate oxide layer
26
and a gate electrode layer
28
. Conventionally, after completing the STI structures
12
and
14
, chemical mechanical polishing (CMP) is employed to level off the surfaces of the gate electrode layer
28
, the STI structures
12
and
14
, and the pad nitride layer
18
.
In
FIG. 1B
, a nitride liner
30
and an oxide cap layer
32
are successively deposited on the substrate
10
, and then the oxide cap layer
32
is removed away from the array area I by using a mask with exposure and wet etching.
Next, in
FIG. 1C
, the pad nitride layer
18
exposed on the array area I is removed, and then a surface reoxidation process is performed thereon. In order to repair a profile loss at the top corner of the gate electrode layer
28
to prevent current leakage therein, a nitride spacer
34
is formed on the top sidewalls of the gate electrode layer
28
, the first STI structure
12
and the second STI structure
14
within the array area I by deposition, photolithography and dry etching. Afterward, an ion implantation process is performed on the array area I.
Next, in
FIG. 1D
, a top oxide layer
36
and an anti-reflective coating (ARC) layer
38
are successively deposited on the substrate.
Next, in
FIG. 1E
, a reactive ion etching (RIE) process is employed to etch back the ARC layer
38
until the top surface of the top oxide layer
36
is leveled off with the top surfaces of the gate electrode layer
28
and the first STI structure
12
.
Next, in
FIG. 1F
, a polysilicon cap layer
38
is patterned on the array area I, and then employed as a mask to remove the nitride liner
30
and the pad nitride layer
18
away from the support area II. Thereafter, a reoxidation process and an ion implantation process are performed on the support area II.
Then, in
FIG. 1G
, a gate dielectric layer
40
and a first gate polysilicon layer
42
are successively deposited on the substrate
10
.
Next, in
FIG. 1H
, a mask, photolithography and etching are used to remove the first gate polysilicon layer
42
and the gate dielectric layer
40
away from the array area I until the gate electrode layer
28
of the vertical transistor
24
is exposed.
Finally, in
FIG. 1I
, a second gate polysilicon layer
44
is patterned on the array area I, thus two gate structures can be defined on the array area I and the support area II, respectively, in subsequent processes.
However, the conventional method has disadvantages described below. First, before the formation of the top oxide layer
36
, the nitride liner
30
and the oxide cap layer
32
are existed on the support area II and the pad nitride layer
18
is removed from the array area I, thus the deposition profile of the top oxide layer
36
presents apparent rise and fall which degrades its planarization result in the subsequent CMP process. Second, since the pad nitride layer
18
is removed from the array area I and the support area II through different steps, extra photolithography and etching processes requiring numbers of masks and excessive photoresist material result in processing difficulties. Third, the polysilicon cap layer
38
is mainly employed to cover the array area I, and then the gate dielectric layer
40
, the first gate polysilicon layer
42
and the polysilicon cap layer
38
must be removed from the array area I, thus increasing process difficulty and production cost.
SUMMARY OF THE INVENTION
The present invention is a fabrication method for a DRAM cell with dual driving voltages and a vertical transistor. More particularly, the fabrication method uses liquid phase deposition (LPD) to integrate an array area process and a support area process in order to simplify steps.
Accordingly, the present invention provides a fabrication method for an array area and a support area of a DRAM cell, including the following steps. A semiconductor silicon substrate is provided with an array area and a support area. Then, a first pad layer and a second pad layer are formed overlying the semiconductor silicon substrate. Next, at least one deep trench is formed in the semiconductor silicon substrate within the array area. A vertical transistor is formed overlying the upper portion of the deep trench, in which the vertical transistor comprises a gate electrode layer. Next, a planarization process is performed to level off the gate electrode layer with the second pad layer. After removing the second pad layer and the first pad layer, a gate dielectric layer is formed overlying the semiconductor silicon substrate. Next, a first gate conductive layer is formed overlying the gate dielectric layer within the support area. Next, a photoresist layer is formed overlying the support area to cover the top and sidewall of the first gate conductive layer. Next, a liquid phase deposition process is performed to deposit a top isolating layer outside the photoresist layer, in which the top isolating layer is formed overlying the gate dielectric layer within the array area. After forming an anti-reflective coating layer on the top isolating layer and the photoresist layer, parts of the anti-reflective coating layer and the top isolating layer are removed until the top isolating layer is leveled with the gate electrode layer. Finally, the photoresist layer is removed.
REFERENCES:
patent: 5665624 (1997-09-01), Hong
Chang Ming-Cheng
Chen Sheng-Tsong
Lin Shian-Jyh
Nanya Technology Corporation
Quintero Law Office
Tsai H. Jey
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