Fabrication method for a vertical MOS transistor

Details Fabrication method for a vertical MOS transistor Fabrication method for a vertical MOS transistor

1999-10-20

2001-02-06

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S328000

Reexamination Certificate

active

06184090

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fabrication method for a vertical metal oxide semiconductor (MOS) transistor. More particularly, the invention relates to a fabrication method for a MOS transistor comprising a vertical channel.
2. Description of the Related Art
In the design for the very large scale integration (VLSI), the dimensions for the transistor device are continuously being reduced to increase the integration. A critical point in the manufacturing of a transistor with small dimension is the reduction of the channel length. To effectively reduce the channel length of a MOS transistor is a very important issue.
Conventionally, the channel length is defined by the photolithography technique. The current photolithography technique development, however, is limited by, for example, the wavelength of the light source, the material and thickness of the photoresist layer, the scattering and deflection properties of light. For the manufacturing of a line width of 0.25 micron and below, it is, therefore, difficult to control the channel length by means of photolithography.
Comparing to the photolithography technique, the development of the thin film deposition and the ion implantation technology are more advance, for example, chemical vapor deposition (CVD) can accurately control the thickness of the deposited thin film to a few angstrom.
SUMMARY OF THE INVENTION
In the light of the foregoing, the present invention provides a fabrication method for a vertical MOS transistor in which the channel length is effectively reduced to raise the integration of the device.
The present invention also provides a fabrication method for a vertical MOS transistor in which the channel length can be accurately controlled.
The present invention further provides a fabrication method for a vertical MOS transistor by using ion implantation to form the source region, the channel region and the drain region and by using deposition to form the gate to accurately control the channel length.
The fabrication method for a vertical MOS transistor according to the present invention includes the following steps. An isolation structure is formed in the substrate to define the active region. Ion implantation is then conducted to form, from the bulk to the surface of the wafer respectively, a first doped layer (for example, a source region), a second doped layer (for example, a channel region) and a third doped layer (for example, a drain region), wherein the dopant of the second doped layer is of a different conductive type than that of the third layer and the first doped layer. Furthermore, the first, second, and third layers are not formed in any particular orders. In another words, as long as the dopant concentration of each doped layer is accurately controlled, the order of forming the doped layers is not pertinent.
Thereafter, a portion of the isolation structure above the first doped layer is removed, exposing the sidewalls of the second doped layer and the third doped layer and the upper surface of the third doped layer, wherein the first doped layer is still being concealed in the substrate. A gate oxide layer is formed on the exposed surface and sidewalls of the second doped layer and the third doped layer. A conductive layer is further formed at the sidewall of second doped layer and on the substrate, covering the isolation structure, wherein the second doped layer and the conductive layer are isolated by the gate oxide layer. This conductive layer can be used as a gate conductive layer.
An important point to note is that the thickness of the gate conductive layer can be controlled to have the same or different thickness from that of the second doped layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5891770 (1999-04-01), Lee
patent: 196 21 244A1 (1996-11-01), None

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