Fabrication method for a two-bit flash memory cell

Details Fabrication method for a two-bit flash memory cell Fabrication method for a two-bit flash memory cell

1999-11-24

2001-10-16

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000

Reexamination Certificate

active

06303439

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for an integrated circuit device. More particularly, the present invention relates to a fabrication method for a two-bit flash memory cell.
2. Description of the Related Art
FIG. 1
is a schematic, cross-sectional view of an EPROM tunnel oxide (ETOX) structure of a flash memory cell according to the prior art. The ETOX structure is basically the addition of a tunnel oxide layer to the traditional erasable and read-only memory cell. As shown in
FIG. 1
, beside an oxide layer not being shown in the Figure, the conventional flash memory cell, as illustrated in
FIG. 1
, comprises a polysilicon gate which is the control gate
104
, a polysilicon layer which is the floating gate
102
, a source region
106
a
and a drain region
106
b
, wherein the source/drain regions
106
a
,
106
b
are formed near the two sides of the floating gate
102
in the substrate
100
.
The method for programming a bit of binary data to a flash memory cell is to apply a positive voltage to the control gate and a lesser positive voltage to the drain region
106
b
(or source region
106
a
) with the source region
106
a
(or drain region
106
b
) being grounded. Hot electrons generated between the drain region
106
b
(or source region
106
a
) and the substrate are injected into and stored in the floating gate
102
. The conventional flash memory cell, however, can only store a data of “1” and “0”, and is thereby known as the single-bit flash memory cell.
A drawback of this type of single-bit flash memory cell is that after the hot electrons are injected into the floating gate
102
, they do not stay at the two ends of the floating gate
102
. The hot electrons tend to redistribute themselves throughout the entire floating gate
102
. The redistribution occurs regardless whether that the hot electrons are injected from the source region
106
a
or from the drain region
106
b
into the floating gate
102
. As a result, the operating mode of this type flash memory cell is limited to a single-bit storage. The occurrence of redistribution not only poses difficulties in the reading operation, it also leads to the serious problem of an over-erase.
SUMMARY OF THE INVENTION
Based on the foregoing, the current invention provides a fabrication method for a two-bit flash memory cell in which a higher integrated flash memory cell can result. The method of the present invention includes forming a shallow trench in a substrate, wherein the trench comprises a left sidewall and a right sidewall. A conformal first oxide layer is then formed on the substrate. Thereafter, a first polysilicon spacer is formed on the tunnel oxide layer that covers the left sidewall of the shallow trench. Concurrently, a second polysilicon spacer is formed on the tunnel oxide layer that covers the right sidewall of the trench. A second oxide layer is then formed on the substrate covering the first polysilicon spacer and the second polysilicon spacer. A second oxide layer is concurrently formed on the substrate. Subsequently, an ion implantation is conducted to form the source/drain region at the two sides of the gate in the substrate.
According to the preferred embodiment of the present invention, the second oxide layer is formed by growing an oxide layer on the first and the second polysilicon spacers via a thermal oxidation process. The first oxide layer, which is not covered by the first and the second polysilicon spacer, would become thicker. A second method in forming the second oxide layer includes deposition.
In another words, the present invention provides a two-bit flash memory cell, wherein the flash memory cell includes a substrate comprising a trench. The trench is sequentially filled with the following components. A conformal first oxide layer is formed on the trench, followed by forming polysilicon spacers on the first oxide layer, which covers the sidewalls of the trench. A second oxide layer is then formed on the polysilicon spacers, to sufficiently cover the polysilicon spacers. A polysilicon gate, excessively filling the shallow trench, is formed on the second oxide layer, wherein a source/drain region is further formed on both sides of the polysilicon gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
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patent: 5567635 (1996-10-01), Acovic et al.
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patent: 5656544 (1997-08-01), Bergendahl et al.
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patent: 5998263 (1999-12-01), Sekariapuram et al.
patent: 6093606 (2000-07-01), Lin et al.

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