Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-08
2001-08-21
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000, C438S238000, C438S253000, C438S396000
Reexamination Certificate
active
06277694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a metal oxide semiconductor (MOS) device comprising a double diffused drain (DDD). More particularly, the present invention relates to a fabrication method for an electrostatic discharge (ESD) protective circuit in a stacked dynamic random access memory (DRAM) device, in which the ESD protection circuit comprises a double diffused drain metal-oxide semiconductor device.
2. Description of the Related Art
During the fabrication of an integrated circuit, such as a dynamic random access memory device or a static random access memory (SRAM) device, or upon the completion of wafer fabrication, static electricity is one of most destructive factors that may induce damage in the integrated circuit. An electrical static discharge (ESD) protection circuit is therefore designed in the wafer to protect the wafer from damage due to external static electricity. Electrostatic damage often occur when a human body comes in contact with an electronic component, generating a high voltage surge, which causes serious damage to the electronic devices. For example, a human body walking on a carpet in a high humidity environment carries an electrostatic charge of about several hundred to about several thousand volts. The electrostatic charge can even exceed ten thousand volts in a low humidity environment. When an electrostatic charge carrier makes contact with a wafer, the electricity is released to the wafer and causes destruction of the wafer.
In the current design of an integrated circuit, the metal oxide semiconductor (MOS) in the integrated circuit comprising a lightly doped drain (LDD) is normally employed to prevent the generation of the hot carrier effect when the device dimensions are being reduced. The lightly doped drain of the metal oxide semiconductor, when being used as an electrical static discharge protection circuit, however, cannot provide the metal oxide semiconductor with sufficient protection from electrostatic discharge. The reason is summarized in the following.
FIG. 1
is a schematic, cross-sectional view of a metal oxide semiconductor comprising a lightly doped source/drain region. Referring to
FIG. 1
, the source/drain region
12
of the metal oxide semiconductor
10
comprises a lightly doped source/drain region
14
. Since the dopant concentration in the lightly doped source/drain region
14
is lower, the electric field in the lightly doped source/drain region
14
is also weaker. As a result, the hot carrier effect generated at the channel
16
area is prevented when the dimensions of the metal oxide semiconductor are reduced.
Protection from electrostatic discharge, however, requires a higher electric field to discharge the high voltage static electrical charge. The metal oxide semiconductor comprising the lightly doped source/drain region mentioned in the above is inadequate for providing protection for an electrostatic discharge because the electric field at the lightly doped source/drain region is too weak.
SUMMARY OF THE INVENTION
Based on the foregoing, the current invention provides a fabrication method for a metal oxide semiconductor having a double-diffused drain, which can be used in an electrostatic discharge protection circuit of a stacked dynamic random access memory device. The fabrication method of the present invention does not require additional masks, and only one additional ion implantation step is needed to complete the fabrication of the electrostatic discharge protection circuit of a double-diffused drain metal oxide semiconductor device and to increase the protective ability of the metal oxide semiconductor from electrostatic discharge.
The current invention provides a fabrication method for a metal oxide semiconductor having a double-diffused drain, which is applicable to the electrostatic discharge protection circuit of a stacked DRAM device. The fabrication method according to the present invention includes providing a substrate, comprising an electrostatic discharge protection circuit or a memory cell region, wherein a first conductive layer and a first mask layer are sequentially formed on the substrate. A portion of the first conductive layer and a portion of the first mask layer are then removed to form, respectively, a first gate and a first source/drain region in the electrostatic discharge protection circuit, and a second gate and a second source/drain region in the memory cell region, wherein the first gate is formed by the second conductive layer and the second mask layer, and the first gate has a first width. A first lightly doped source/drain region which comprises a lightly doped and a second lightly doped source/drain region are formed, respectively, in the electrostatic discharge protection circuit region and the memory cell region. A first dielectric layer is then formed on the substrate, wherein the first dielectric layer comprises an opening to expose the first gate and a portion of the first source/drain region, and a second opening to expose a portion of the second source/drain region. A third conductive layer is then formed on the first dielectric layer, filling the first opening and the second opening. The third conductive layer is then patterned to form a third gate in the first source/drain region, and to form a second conductive layer in the second opening which is electrically connected to the second source/drain region in the second opening, wherein the third gate has a second width which is smaller than the first width. An ion implantation is further conducted to form a double-diffused drain region in the first source/drain region. Subsequently, the second dielectric layer is formed on the first dielectric layer, filling the first opening. A capacitor is further formed in the second dielectric layer of the memory cell region to electrically connect with the second source/drain region. Thereafter, a third dielectric layer is formed on the second dielectric layer. A conductive line is further formed in the third dielectric layer of the electrostatic discharge protection circuit region, wherein the conductive line is electrically connected with the first source/drain region of the double-diffused drain region.
According to the present invention, the formation of a MOS comprising a double-diffused source/drain region increases the electric field at the gate channel region, allowing the gate channel region to withstand the high voltage of the static electrical charge and to increase the preventive capability of the metal oxide semiconductor from electrostatic discharge. Furthermore, the fabrication method of the present invention does not require additional masks; only an extra ion implantation step is sufficient to form an electrostatic discharge protection circuit, which uses a double-diffused drain metal oxide semiconductor device. The electrostatic discharge prevention capability of the electrostatic discharge circuit is thereby enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5246872 (1993-09-01), Mortensen
patent: 5920774 (1999-07-01), Wu
patent: 6008081 (1999-12-01), Wu
patent: 6187619 (2001-02-01), Wu
Bowers Charles
Sarkar Asok Kumar
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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