Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-26
2001-08-14
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S286000
Reexamination Certificate
active
06274430
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89113550, filed Jul. 7, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a non-volatile memory device. More particularly, the present invention relates to a fabrication method for an electrically erasable programmable read only memory device that has a high breakdown voltage.
2. Description of the Related Art
In the conventional non-volatile memory device, which includes the erasable programmable read only memory (EPROM) device, the electrically erasable programmable read only memory (EEPROM) device and the flash memory device, the stored memory or data is retained and is not being erased during the shortage of the power supply. These types of memory devices thus possess a superior information storage characteristic, and the research for the development in this area continues.
An electrically erasable programmable read only memory is one type of the non-volatile memory devices. In general, an EEPROM cell comprises two gates, which includes a floating gate formed with polysilicon for charge storage and a control gate to control the retrieval of information. The floating gate is normally maintained in a “floating” condition and is not connected to any circuitry, whereas the control gate is normally connected to the word line. The EEPROM cell further includes a tunnel oxide layer and a dielectric layer formed between the substrate and the floating gate, and between the floating gate and the control gate, respectively. In addition, source/drain regions are formed in the substrate on both sides of the control gate.
The peripheral high voltage circuit region device, used to connect the EEPROM and the peripheral circuit, requires withstanding a higher voltage when the electrical erasure or the programming process is performed. However, under the current trend of a higher integration, the device dimension is reduced according to the design rule. The device dimension for the peripheral high voltage circuit region decreases correspondingly. Since under a normal high voltage operation, the thickness of the device gate oxide layer for the peripheral high voltage circuit region can not be easily reduced. Similarly, the channel length of the peripheral high voltage circuit region can not be reduced. The difficulty for fabricating an electrically erasable programmable read only memory device is thereby greatly increased.
Furthermore, during the operation of a memory transistor, the higher the gate-coupling ratio between the floating gate and the control gate, the working voltage for an operation is lower. The gate-coupling ratio between the floating gate and the control thus needs to be increased.
Approaches to increase the gate-coupling ratio include increasing the overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the dielectric constant (k) of the dielectric layer between the floating gate and the control gate. The thickness of the dielectric layer between the floating gate and the control gate, however, must maintain a certain thickness to prevent an entry of the electrons trapped in the floating gate into the control gate, leading to an ineffective device. Since increasing the dielectric constant of the dielectric layer between the floating gate and the control gate involves issues such as replacing the processing equipment and the maturity or immaturity of the current technology, the approach of increasing the dielectric constant of the dielectric layer can not be easily achieved.
SUMMARY OF THE INVENTION
Based on the foregoing, a fabrication method for a high voltage electrically erasable programmable read only memory device is provided. According to one preferred embodiment of the present invention, a substrate comprising a memory device region, a peripheral low voltage circuit region and a peripheral high voltage circuit region is provided. A floating gate is formed on the substrate in the memory device region, while a gate electrode is formed on the substrate in the peripheral high voltage circuit region. A layer of oxide
itride/oxide is then formed on the substrate, wherein the oxide
itride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer. The second oxide layer located in the peripheral high voltage circuit region is then removed, followed by removing the nitride layer in the peripheral high voltage circuit region. Thereafter, an oxidation process on the second oxide layer of the peripheral high voltage circuit region and a double diffused drain implantation process are conducted to form a bird's beak structure at the bottom corners of the gate electrode, and a double diffused drain structure in the substrate on both sides of the gate electrode, respectively. A control gate is then formed on the oxide
itride/oxide layer on the memory device region. Subsequently, a source/drain region is formed in the substrate on both sides of the gate electrode in the peripheral low voltage circuit region.
The present invention provides a fabrication method for a high breakdown voltage electrically erasable programmable read only memory device. Since a bird's beak structure is formed at the bottom corners of the gate electrode in the peripheral high voltage circuit region, the bottom comers of the gate electrode thus become rounded to increase the thickness of the gate oxide layer at the bottom comers of the gate electrode. The concentration of the electric field at the bottom comers of the gate electrode is thereby reduced. Furthermore, the breakdown voltage of the gate structure in the peripheral high voltage circuit region is increased without reducing the thickness of the gate oxide layer.
In addition, the floating gate of the present invention is completely enclosed by the oxide
itride/oxide layer to increase the gate-coupling ratio (GCR) between the control gate and the floating gate.
Furthermore, the rounding of the bottom comers of the gate electrode in the peripheral high voltage circuit region is formed along with the formation the gate oxide layer in the low voltage circuit region. The driving-in process for the double diffused drain structure can also be accomplished by the same process used for the rounding of bottom comers of the gate electrode. Thus, no additional thermal budget is required.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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patent: 5674762 (1997-10-01), See et al.
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patent: 5963808 (1999-10-01), Lu et al.
patent: 5976934 (1999-10-01), Hayakawa
patent: 6023085 (2000-02-01), Fang
patent: 6087211 (2000-07-01), Kalnitsky et al.
Hsu Sung-Mu
Jan Yi-Peng
Chaudhari Chandra
United Microelectronics Corp.
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