Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-04
1998-12-01
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, 438397, H01L 218242
Patent
active
058438211
ABSTRACT:
The present invention provides a method of manufacturing a capacitor for a high density memory device. The capacitor has a bottom electrode 70 having cylindrical walls 54A more closely spaced than the minimum photolithography dimensions. The method begins by providing a first conductive layer 30 that contacts the substrate. A polyoxide layer 36A is used to form an opening over the first conductive layer 30 that defines a dielectric stud 50. An important feature is the polyoxide layer 36A makes the opening 38A smaller than the photolithographic limits. Cylindrical walls 54A are formed on the sidewalls of the dielectric stud 50. Subsequent etches are used to form the bottom electrode 54A, 30B (70). The electrode of the present invention is smaller than the conventional minimum photo ground rules and the method is cost effective and highly manufacturable.
REFERENCES:
patent: 5266512 (1993-11-01), Kirsch
patent: 5545582 (1996-08-01), Roh
patent: 5552334 (1996-09-01), Tseng
patent: 5554557 (1996-09-01), Koh
patent: 5578516 (1996-11-01), Chou
patent: 5583069 (1996-12-01), Ahn et al.
Ackerman Stephen B.
Chang Joni
Saile George O.
Stoffel William J.
Vanguard International Semiconductor Corporation
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