Fabrication method for a compact DRAM cell

Details Fabrication method for a compact DRAM cell Fabrication method for a compact DRAM cell

2000-03-28

2001-04-17

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S596000

Reexamination Certificate

active

06218241

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method for a compact DRAM cell.
2. Description of the Related Art
There is a continuing effort in the semiconductor industry to increase the integration density on a semiconductor device, for example, a Dynamic Random Access Memory device. The DRAM device is composed, in part, of an array of memory cells. Each DRAM cell is formed with a single pass transistor, typically a field effect transistor (FET) and a storage capacitor. The storage capacitor makes contact to one of the two source/drain areas of the FET and a bit line makes contact to the other source/drain area of each of the FET transistors.
There have been, however, many problems in developing highly integrated memory devices due to the physically imposed limitations of the semiconductor fabrication equipments and the semiconductor device itself. For example, in order to achieve a highly integrated memory device, there should be a decreased area for the DRAM cell. The bit line and the node contacts to the FET source/drain areas on the substrate must also be correspondingly reduced in size and are hence formed increasingly closer together. The scale down of the cell size, however, is limited by the alignment of the contact openings to the pass gate. A reduction of the cell dimension would normally result in a decrease of the processing window, and due to the resolution limitation of the current photolithography techniques, there is an increased risk factor that the insulation structure is etched leading to a current leakage. Especially in semiconductor device with Ultra Large Scale Integration over 256 Megabit DRAM, new technology is needed for forming a contact opening capable of securing an alignment margin for maintaining the insulation of the conductors because the width between the word lines and the width between the bit lines are as narrow as a minimum line width. Furthermore, a sufficient channel length must be maintained to provide the required current driving capability for the pass transistor. The increase in the device integration is thus inevitably followed by the problems of the current leakage and shorting of the conductors.
To better understand the nature of the problem in reducing the cell size, the fabrication of a DRAM cell according to the conventional practice is shown schematically in cross-sectional view in
FIGS. 1A
to
1
E.
As shown in
FIG. 1A
, a semiconductor substrate
100
having isolation structures
102
formed thereon, such as the shallow trench isolation structures (STI) is provided. The isolation structures
102
partition the substrate
100
into active and non-active parts. Transistors
104
and
106
are formed on the substrate
100
. The transistors
104
and
106
consist of a gate conductive layer
108
, a gate oxide layer
110
, source/drain part
112
, a cap layer
116
and a silicon nitride spacer
114
.
Referring to
FIG. 1B
, a dielectric layer
118
is formed over the substrate
100
covering the transistors
104
,
106
and the isolating structures
102
. Photolithgraphy and etching are then conducted to pattern the dielectric layer
118
to form a contact opening
120
, exposing the source/drain part
112
. A polysilicon layer
122
is further deposited into the contact opening
120
over the dielectric layer
118
.
As shown in
FIG. 1C
, photolithography and etching are conducted again to pattern the polysilicon layer
122
to form a bit line
124
in the contact opening
120
. Another dielectric layer
126
is formed over the dielectric layer
118
.
Referring to
FIG. 1D
, the dielectric layers
126
and
118
are then patterned to form a node contact opening
128
.
Continuing to
FIG. 1E
, a contact plug
130
is formed inside the node contact opening
128
. A bottom electrode
134
is further formed over the contact plug
130
.
As the level of integration of devices continues to increase, the bit line contact opening
120
and the node contact opening
128
are formed increasingly closer to each other, resulting in a shorting between the conductors to occur more frequently. Furthermore, due to the spatial resolution resulting from the light source used in photolithography, the alignment precision in forming the contact openings becomes limited. If the contact openings
128
are slightly misaligned, a portion of the isolating structure
102
may be etched leading to a leakage current. Additionally, as the device dimension decreases, the channel length must be correspondingly reduced in size. The short channel effect would become significant.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides a fabrication method for a compact DRAM cell, wherein the cell size may be reduced without compromising the channel length or the alignment margin of the contacts to the pass gate.
The present invention also provides a method of manufacturing a semiconductor device which is capable of securing the node contact and the bit line contact alignment margins so as to prevent the occurrence of the shorting phenomenon and the current leakage problem.
The present invention further provides a method for increasing the integration of a semiconductor device, wherein the channel length is scalable and is not restricted by the resolution limitations of the current photolithographic techniques.
In accordance with the present invention, as embodied and broadly described herein, a semiconductor substrate is provided. A gate insulating layer is then formed on the substrate, followed by sequentially forming a first doped polysilicon layer, a metal barrier layer, a second doped polysilicon layer, a metal silicide layer, a first oxide layer on the gate insulating layer. The first oxide layer is then patterned to expose a part of a surface of the metal silicide layer. Thereafter, a first silicon nitride spacer is formed on the side of the patterned first silicon oxide layer. The patterned first silicon oxide layer is further removed.
Subsequently, parts of the metal silicide layer, the second doped polysilicon layer, the metal barrier layer using the first silicon nitride spacer as a mask, wherein the first silicon nitride spacer and remaining parts of the metal silicide layer, the second doped polysilicon layer, the metal barrier layer form an upper of a pass gate. A second silicon nitride spacer is then formed on the sidewall of the upper part of the gate. After this, parts of the first doped polysilicon layer and the gate insulating layer are removed using the second silicon nitride spacer as a mask, wherein a remaining part of the first doped polysilcion layer and the underlying gate insulating layer form a lower part of the gate. A bit line contact subsequently formed on one side of the gate, wherein the bit line contact is formed above the lower part of the gate. A node contact is also formed on other side of the gate, wherein the node contact is also formed above the lower part of the gate.
According to this preferred embodiment of the present invention, the pass gate is formed with a narrow upper part and a wide lower part. An adequate channel length is thus maintained. Since the upper part of the pass gate is narrower, the contact openings can form closer to the pass gate without compromising the alignment margin of the contact openings to the pass gate. The potential problem of etching the insulation structure and leading to a current leakage is thus prevented. Furthermore, since the size of the pass gate is determined by the widths of the silicon nitride spacers, the manufacturing of the pass gate is easier to control. The pass gate can form having a considerable smaller feature size, and is not limited by the current lithographic resolution.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 59306

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