Fabricating semiconductor memory devices with improved cell isol

Details Fabricating semiconductor memory devices with improved cell isol Fabricating semiconductor memory devices with improved cell isol

1997-04-25

2000-07-25

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438297, 438439, 257314, 257316, 257509, H01L 21336

Patent

active

060936037

ABSTRACT:
A method of fabricating semiconductor memory devices which has sufficient cell isolation to achieve miniaturization at the 0.3 to 0.4 .mu.m level. In the semiconductor memory devices of the present application miniaturization is achieved by removing overlap allowances between each gate and each LOCOS and those between each diffusion layer and each LOCOS used to separate the above-described semiconductor memory elements. In one embodiment, the method according to the present application includes forming LOCOSs in forms of stripes in parallel with a direction in which a select gate is formed in forming the LOCOSs for separating respective semiconductor memory elements, forming laminated gate portions each including a floating gate and a control gate perpendicularly to the LOCOSs, forming strip-shaped resist layers in parallel with the select gate so as to cover portions to be selection transistors and a part of the upper regions in the selection transistor side of the above laminated gate portions, etching the LOCOSs by using the resist layers and the laminated gate portions as masks, forming impurity diffusion layers to be source lines and drain lines by using the above resist layers and the above laminated gate portions as masks, and then forming select gates, and therefore it does not need the mask matching allowances between the laminated gates and the LOCOSs nor the mask matching allowances between the source diffusion layers and the LOCOSs which have conventionally prevented the miniaturization due to its self-alignment feature. In addition, patterning is performed by combinations of strip and therefore the corners of the LOCOSs are not rounded off so as to decrease the mask matching allowances between the floating gates and the LOCOSs.

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